[raggedstone] / ethernet / source / pci / pci_spoci_ctrl.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: pci_spoci_ctrl                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free; you can redistribute it            ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_spoci_ctrl.v,v $
// Revision 1.1  2007-03-20 17:50:56  sithglan
// add shit
//
// Revision 1.1  2004/01/24 11:54:18  mihad
// Update! SPOCI Implemented!
//
//

`include "pci_constants.v"

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module pci_spoci_ctrl
(
    reset_i             ,
    clk_i               ,
                        
    do_rnd_read_i       ,
    do_seq_read_i       ,
    do_write_i          ,
                        
    write_done_o        ,
    dat_rdy_o           ,
    no_ack_o            ,
                        
    adr_i               ,
    dat_i               ,
    dat_o               ,

    pci_spoci_sda_i     ,
    pci_spoci_sda_oe_o  ,
    pci_spoci_scl_oe_o
);

parameter tx_rx_state_width = 9     ;
parameter tx_rx_idle        = 'h1   ;
parameter tx_rx_start       = 'h2   ;
parameter tx_rx_restart     = 'h4   ;
parameter tx_rx_send_bits   = 'h8   ;
parameter tx_rx_rec_bits    = 'h10  ;
parameter tx_rx_send_ack    = 'h20  ;
parameter tx_rx_rec_ack     = 'h40  ;
parameter tx_rx_send_nack   = 'h80  ;
parameter tx_rx_stop        = 'h100 ;

parameter rw_seq_state_width    = 5     ;
parameter rw_seq_idle           = 'h1   ;
parameter rw_seq_tx_ctrl        = 'h2   ;
parameter rw_seq_tx_adr         = 'h4   ;
parameter rw_seq_tx_byte        = 'h8   ;
parameter rw_seq_rx_byte        = 'h10  ;

`ifdef PCI33
parameter cnt_width     = 9     ;
parameter period_cnt    = 334   ;
`endif

`ifdef PCI66
parameter cnt_width     = 10    ;
parameter period_cnt    = 667   ;
`endif

input   reset_i ,
        clk_i   ;

input   do_rnd_read_i   ,
        do_seq_read_i   ,
        do_write_i      ;

output  write_done_o    ,
        dat_rdy_o       ,
        no_ack_o        ;

input   [10: 0] adr_i   ;
input   [ 7: 0] dat_i   ;
output  [ 7: 0] dat_o   ;

input   pci_spoci_sda_i     ;

output  pci_spoci_sda_oe_o  ,
        pci_spoci_scl_oe_o  ;

reg write_done_o    ,
    dat_rdy_o       ,
    no_ack_o        ;

reg [ 7: 0] dat_o   ;

reg pci_spoci_sda_oe_o  ,
    pci_spoci_scl_oe_o  ;

reg clk_gen_cnt_en  ;
reg clk_gen_cnt_clr ;
reg [cnt_width - 1:0] clk_gen_cnt   ;

reg [tx_rx_state_width - 1:0] tx_rx_state       ;
reg [tx_rx_state_width - 1:0] tx_rx_next_state  ;
reg tx_rx_sm_idle ;

reg scl_oe      ;
reg scl_oe_en   ;
reg sda_oe      ;
reg sda_oe_en   ;

reg sda_i_reg_en    ;
reg sda_i_reg       ;

always@(posedge clk_i or posedge reset_i)
begin
    if (reset_i)
    begin
        clk_gen_cnt <= 'h0  ;

        tx_rx_state <= tx_rx_idle   ;

    `ifdef ACTIVE_LOW_OE
        pci_spoci_sda_oe_o <= 1'b1 ;
        pci_spoci_scl_oe_o <= 1'b1 ;
    `endif

    `ifdef ACTIVE_HIGH_OE
        pci_spoci_sda_oe_o <= 1'b0 ;
        pci_spoci_scl_oe_o <= 1'b0 ;
    `endif

        sda_i_reg <= 1'b1 ;
    end
    else
    begin
        tx_rx_state <= tx_rx_next_state ;
        
        if (clk_gen_cnt_clr)
            clk_gen_cnt <= 'h0  ;
        else if (clk_gen_cnt_en)
            clk_gen_cnt <= clk_gen_cnt + 1'b1 ;

    
        if (sda_oe_en)
        begin
        `ifdef ACTIVE_LOW_OE
            pci_spoci_sda_oe_o <= ~sda_oe   ;
        `endif

        `ifdef ACTIVE_HIGH_OE
            pci_spoci_sda_oe_o <= sda_oe    ;
        `endif
        end

        if (scl_oe_en)
        begin
        `ifdef ACTIVE_LOW_OE
            pci_spoci_scl_oe_o <= ~scl_oe   ;
        `endif

        `ifdef ACTIVE_HIGH_OE
            pci_spoci_scl_oe_o <= scl_oe    ;
        `endif
        end

        if (sda_i_reg_en)
            sda_i_reg <= pci_spoci_sda_i ;
    end
end

reg [ 7: 0] tx_shift_reg ;

reg send_start  ;
reg start_sent  ;

reg send_bit    ;
reg bit_sent    ;

reg rec_bit     ;
reg bit_rec     ;

reg rec_ack     ;
reg ack_rec     ;
reg nack_rec    ;

reg send_ack    ;
reg ack_sent    ;
reg send_nack   ;
reg nack_sent   ;

reg send_stop   ;
reg stop_sent   ;

always@
(
    tx_rx_state     or
    clk_gen_cnt     or
    send_start      or
    send_bit        or
    tx_shift_reg    or
    send_stop       or
    rec_ack         or
    sda_i_reg       or
    rec_bit         or
    send_ack        or
    send_nack
)
begin
    clk_gen_cnt_clr     = 1'b0          ;
    clk_gen_cnt_en      = 1'b0          ;
    tx_rx_next_state    = tx_rx_state   ;
    tx_rx_sm_idle       = 1'b0          ;
    scl_oe              = 1'b0          ;
    sda_oe              = 1'b0          ;
    scl_oe_en           = 1'b0          ;
    sda_oe_en           = 1'b0          ;
    start_sent          = 1'b0          ;
    bit_sent            = 1'b0          ;
    ack_rec             = 1'b0          ;
    nack_rec            = 1'b0          ;
    sda_i_reg_en        = 1'b0          ;
    stop_sent           = 1'b0          ;
    bit_rec             = 1'b0          ;
    ack_sent            = 1'b0          ;
    nack_sent           = 1'b0          ;

    case (tx_rx_state)

    tx_rx_idle:
    begin
        tx_rx_sm_idle = 1'b1 ;

        // from idle state, the only transition can be to the send start bit
        if (send_start)
        begin
            tx_rx_next_state = tx_rx_start  ;
            clk_gen_cnt_clr  = 1'b1         ;
        end
    end

    tx_rx_start:
    begin
        clk_gen_cnt_en  = 1'b1  ;
        sda_oe          = 1'b1  ;

        // start bit is sent by transmiting 0 on the sda line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            start_sent = 1'b1 ;
            sda_oe_en  = 1'b1 ;
        end
        
        // after half clock period of driving the sda low, the only possible
        // transition is to send state.
        // if send bit is not active, stop the procedure - undrive sda
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;
            if (send_bit)
            begin
                tx_rx_next_state = tx_rx_send_bits ;
            end
            else
            begin
                sda_oe              = 1'b0          ;
                sda_oe_en           = 1'b1          ;
                tx_rx_next_state    = tx_rx_idle    ;
            end
        end
    end

    tx_rx_send_bits:
    begin
        clk_gen_cnt_en = 1'b1 ;

        // generate high to low transition on the scl line immediately
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, load new value for sda oe, depending on the
        // msb bit in the shift register
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = ~tx_shift_reg[7]  ;
            sda_oe_en   = 1'b1              ;
            bit_sent    = 1'b1              ;
        end

        // after clock low time, generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after clock high time, check what to do next
        if (clk_gen_cnt == (period_cnt))
        begin
            clk_gen_cnt_clr = 1'b1 ;

            if (~send_bit)
            begin
                // after transmiting all the bits, the only possible transition is to the state
                // that checks the eprom acknowledge
                if (rec_ack)
                    tx_rx_next_state = tx_rx_rec_ack ;
                else
                begin
                    sda_oe              = 1'b0          ;
                    sda_oe_en           = 1'b1          ;
                    tx_rx_next_state    = tx_rx_idle    ;
                end
            end
        end
    end

    tx_rx_rec_bits:
    begin
        clk_gen_cnt_en = 1'b1 ;
        sda_i_reg_en   = 1'b1 ;

        // generate high to low transition on the scl line immediately
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, disable sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end

        // after clock low time, generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock high time, report received bit
        if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
        begin
            bit_rec = 1'b1  ;
        end

        // after clock period is finished, check the next operation
        if (clk_gen_cnt == (period_cnt))
        begin
            clk_gen_cnt_clr = 1'b1 ;

            if (~rec_bit)
            begin
                // when all bits are received, only nack or ack next states are possible
                if (send_ack)
                    tx_rx_next_state = tx_rx_send_ack   ;
                else if (send_nack)
                    tx_rx_next_state = tx_rx_send_nack  ;
                else
                begin
                    tx_rx_next_state = tx_rx_idle    ;
                end
            end
        end
    end

    tx_rx_send_ack:
    begin
        clk_gen_cnt_en  = 1'b1  ;

        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, enable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b1  ;
            sda_oe_en   = 1'b1  ;
            ack_sent    = 1'b1  ;
        end

        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;

            // after the byte is acknowledged, the only possible next state is receive bits
            // state
            if (rec_bit)
                tx_rx_next_state = tx_rx_rec_bits   ;
            else
            begin
                // this should never happen
                sda_oe      = 1'b0  ;
                sda_oe_en   = 1'b1  ;

                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end

    tx_rx_rec_ack:
    begin

        clk_gen_cnt_en  = 1'b1  ;
        sda_i_reg_en    = 1'b1  ;

        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, disable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end

        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after 1/2 clock high time, report ack or nack condition, depending on the sda input state
        if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
        begin
            ack_rec     = ~sda_i_reg ;
            nack_rec    =  sda_i_reg ;
        end

        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;

            if (send_bit)
                tx_rx_next_state = tx_rx_send_bits  ;
            else if (rec_bit)
                tx_rx_next_state = tx_rx_rec_bits   ;
            else if (send_stop)
                tx_rx_next_state = tx_rx_stop       ;
            else if (send_start)
                tx_rx_next_state = tx_rx_restart    ;
            else
            begin
                // this should never happen
                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end

    tx_rx_send_nack:
    begin
        clk_gen_cnt_en  = 1'b1  ;

        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, disable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
            nack_sent   = 1'b1  ;
        end

        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;

            // after the no acknowledge is sent, the only possible next state is stop
            // state
            if (send_stop)
                tx_rx_next_state = tx_rx_stop   ;
            else
            begin
                // this should never happen
                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end

    tx_rx_restart:
    begin
        clk_gen_cnt_en = 1'b1 ;

        // generate high to low transition
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, release sda line
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end

        // generate low to high transition
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            clk_gen_cnt_clr = 1'b1 ;

            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;

            if (send_start)
                tx_rx_next_state = tx_rx_start ;
            else
                tx_rx_next_state = tx_rx_idle ;
        end
    end

    tx_rx_stop:
    begin
        clk_gen_cnt_en = 1'b1 ;

        // generate high to low transition
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end

        // after half of clock low time, drive sda line low
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b1  ;
            sda_oe_en   = 1'b1  ;
        end

        // generate low to high transition
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end

        // after full clock period, release the sda line
        if (clk_gen_cnt == period_cnt)
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
            stop_sent   = 1'b1  ;

            tx_rx_next_state = tx_rx_idle ;
        end
    end

    endcase
end

reg [rw_seq_state_width - 1:0]  rw_seq_state    ;

reg doing_read      , 
    doing_write     , 
    doing_seq_read  ,
    adr_set         ;

reg [ 3: 0] bits_transfered ;

always@(posedge clk_i or posedge reset_i)
begin
    if (reset_i)
    begin
        rw_seq_state    <= rw_seq_idle  ;
        adr_set         <= 1'b0         ;
        doing_read      <= 1'b0         ;
        doing_write     <= 1'b0         ;
        doing_seq_read  <= 1'b0         ;
        dat_o           <= 'h0          ;
        tx_shift_reg    <= 'h0          ;
        send_start      <= 'h0          ;
        send_stop       <= 'h0          ;
        send_bit        <= 'h0          ;
        send_nack       <= 'h0          ;
        rec_ack         <= 'h0          ;
        no_ack_o        <= 'h0          ;
        bits_transfered <= 'h0          ;
        write_done_o    <= 'h0          ;
        dat_rdy_o       <= 'h0          ;
        send_ack        <= 'h0          ;
        rec_bit         <= 'h0          ;
    end
    else
    begin

        case (rw_seq_state)
            
        rw_seq_idle:
        begin
            tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ;
            adr_set      <= 1'b0                          ;

            if ( tx_rx_sm_idle & ~(doing_write | doing_read | doing_seq_read) )
            begin
                if (do_write_i | do_rnd_read_i | do_seq_read_i)
                begin
                    rw_seq_state <= rw_seq_tx_ctrl  ;
                    send_start   <= 1'b1            ;
                end

                if (do_write_i)
                    doing_write     <= 1'b1 ;
                else if (do_rnd_read_i)
                    doing_read      <= 1'b1 ;
                else if (do_seq_read_i)
                    doing_seq_read  <= 1'b1 ;
            end
            else
            begin
                doing_write     <= 1'b0 ;
                doing_read      <= 1'b0 ;
                doing_seq_read  <= 1'b0 ;
            end
        end
    
        rw_seq_tx_ctrl:
        begin
            if (send_start)
            begin
                bits_transfered <= 'h0 ;

                if (start_sent)
                begin
                    send_start <= 1'b0 ;
                    send_bit   <= 1'b1 ;
                end
            end
            else if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end

                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;

                if (ack_rec | nack_rec)
                    rec_ack <= 1'b0 ;

                if (ack_rec)
                begin
                    if (doing_write | ~adr_set)
                    begin
                        rw_seq_state    <= rw_seq_tx_adr    ;
                        tx_shift_reg    <= adr_i[ 7: 0]     ;
                        send_bit        <= 1'b1             ;
                    end
                    else
                    begin
                        rw_seq_state    <= rw_seq_rx_byte   ;
                        rec_bit         <= 1'b1             ;
                    end
                end
                else if (nack_rec)
                begin
                    no_ack_o    <= 1'b1 ;
                    send_stop   <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                no_ack_o <= 1'b0 ;

                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
    
        rw_seq_tx_adr:
        begin
            if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end

                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;

                if (ack_rec | nack_rec)
                    rec_ack <= 1'b0 ;

                if (ack_rec)
                begin

                    adr_set <= 1'b1 ;

                    if (doing_write)
                    begin
                        send_bit        <= 1'b1             ;
                        rw_seq_state    <= rw_seq_tx_byte   ;
                        tx_shift_reg    <= dat_i            ;
                    end
                    else if (doing_read | doing_seq_read)
                    begin
                        send_start      <= 1'b1             ;
                        rw_seq_state    <= rw_seq_tx_ctrl   ;
                        tx_shift_reg    <= 8'b10100001      ;
                    end
                end
                else if (nack_rec)
                begin
                    no_ack_o    <= 1'b1 ;
                    send_stop   <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                no_ack_o    <= 1'b0 ;

                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
    
        rw_seq_tx_byte:
        begin
            if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end

                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;

                if (ack_rec | nack_rec)
                begin
                    rec_ack   <= 1'b0   ;
                    send_stop <= 1'b1   ;
                end

                if (nack_rec)
                    no_ack_o <= 1'b1 ;

                if (ack_rec)
                    write_done_o <= 1'b1 ;
            end
            else if (send_stop)
            begin
                no_ack_o        <= 1'b0 ;
                write_done_o    <= 1'b0 ;

                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
    
        rw_seq_rx_byte:
        begin
            if (rec_bit)
            begin
                if (bit_rec)
                begin
                    bits_transfered <= bits_transfered + 1'b1   ;
                    dat_o           <= {dat_o[6:0], sda_i_reg}  ;
                end

                if (bits_transfered == 'h8)
                begin
                    rec_bit   <= 1'b0 ;
                    dat_rdy_o <= 1'b1 ;
                    if (doing_read)
                        send_nack <= 1'b1 ;
                    else
                        send_ack  <= 1'b1 ;
                end
            end
            else if (send_nack)
            begin
                dat_rdy_o       <= 1'b0 ;
                bits_transfered <= 'h0  ;

                if (nack_sent)
                begin
                    send_stop <= 1'b1 ;
                    send_nack <= 1'b0 ;
                end
            end
            else if (send_ack)
            begin
                dat_rdy_o       <= 1'b0 ;
                bits_transfered <= 'h0  ;

                if (~do_seq_read_i)
                begin
                    send_ack    <= 1'b0 ;
                    send_nack   <= 1'b1 ;
                end
                else if (ack_sent)
                begin
                    send_ack <= 1'b0 ;
                    rec_bit  <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                if (stop_sent)  
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
        endcase
    end
end

endmodule // pci_spoci_ctrl
Commit	Line	Data
40a1f26c	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// File name: pci_spoci_ctrl ////
	4	//// ////
	5	//// This file is part of the "PCI bridge" project ////
	6	//// http://www.opencores.org/cores/pci/ ////
	7	//// ////
	8	//// Author(s): ////
	9	//// - Miha Dolenc (mihad@opencores.org) ////
	10	//// ////
	11	//// ////
	12	//////////////////////////////////////////////////////////////////////
	13	//// ////
	14	//// Copyright (C) 2004 Miha Dolenc, mihad@opencores.org ////
	15	//// ////
	16	//// This source file may be used and distributed without ////
	17	//// restriction provided that this copyright statement is not ////
	18	//// removed from the file and that any derivative work contains ////
	19	//// the original copyright notice and the associated disclaimer. ////
	20	//// ////
	21	//// This source file is free; you can redistribute it ////
	22	//// and/or modify it under the terms of the GNU Lesser General ////
	23	//// Public License as published by the Free Software Foundation; ////
	24	//// either version 2.1 of the License, or (at your option) any ////
	25	//// later version. ////
	26	//// ////
	27	//// This source is distributed in the hope that it will be ////
	28	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	29	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	30	//// PURPOSE. See the GNU Lesser General Public License for more ////
	31	//// details. ////
	32	//// ////
	33	//// You should have received a copy of the GNU Lesser General ////
	34	//// Public License along with this source; if not, download it ////
	35	//// from http://www.opencores.org/lgpl.shtml ////
	36	//// ////
	37	//////////////////////////////////////////////////////////////////////
	38	//
	39	// CVS Revision History
	40	//
	41	// $Log: pci_spoci_ctrl.v,v $
	42	// Revision 1.1 2007-03-20 17:50:56 sithglan
	43	// add shit
	44	//
	45	// Revision 1.1 2004/01/24 11:54:18 mihad
	46	// Update! SPOCI Implemented!
	47	//
	48	//
	49
	50	`include "pci_constants.v"
	51
	52	// synopsys translate_off
	53	`include "timescale.v"
	54	// synopsys translate_on
	55
	56	module pci_spoci_ctrl
	57	(
	58	reset_i ,
	59	clk_i ,
	60
	61	do_rnd_read_i ,
	62	do_seq_read_i ,
	63	do_write_i ,
	64
65	write_done_o ,
66	dat_rdy_o ,
67	no_ack_o ,
68
69	adr_i ,
70	dat_i ,
71	dat_o ,
72
73	pci_spoci_sda_i ,
74	pci_spoci_sda_oe_o ,
75	pci_spoci_scl_oe_o
76	);
77
78	parameter tx_rx_state_width = 9 ;
79	parameter tx_rx_idle = 'h1 ;
80	parameter tx_rx_start = 'h2 ;
81	parameter tx_rx_restart = 'h4 ;
82	parameter tx_rx_send_bits = 'h8 ;
83	parameter tx_rx_rec_bits = 'h10 ;
84	parameter tx_rx_send_ack = 'h20 ;
85	parameter tx_rx_rec_ack = 'h40 ;
86	parameter tx_rx_send_nack = 'h80 ;
87	parameter tx_rx_stop = 'h100 ;
88
89	parameter rw_seq_state_width = 5 ;
90	parameter rw_seq_idle = 'h1 ;
91	parameter rw_seq_tx_ctrl = 'h2 ;
92	parameter rw_seq_tx_adr = 'h4 ;
93	parameter rw_seq_tx_byte = 'h8 ;
94	parameter rw_seq_rx_byte = 'h10 ;
95
96	`ifdef PCI33
97	parameter cnt_width = 9 ;
98	parameter period_cnt = 334 ;
99	`endif
100
101	`ifdef PCI66
102	parameter cnt_width = 10 ;
103	parameter period_cnt = 667 ;
104	`endif
105
106	input reset_i ,
107	clk_i ;
108
109	input do_rnd_read_i ,
110	do_seq_read_i ,
111	do_write_i ;
112
113	output write_done_o ,
114	dat_rdy_o ,
115	no_ack_o ;
116
117	input [10: 0] adr_i ;
118	input [ 7: 0] dat_i ;
119	output [ 7: 0] dat_o ;
120
121	input pci_spoci_sda_i ;
122
123	output pci_spoci_sda_oe_o ,
124	pci_spoci_scl_oe_o ;
125
126	reg write_done_o ,
127	dat_rdy_o ,
128	no_ack_o ;
129
130	reg [ 7: 0] dat_o ;
131
132	reg pci_spoci_sda_oe_o ,
133	pci_spoci_scl_oe_o ;
134
135	reg clk_gen_cnt_en ;
136	reg clk_gen_cnt_clr ;
137	reg [cnt_width - 1:0] clk_gen_cnt ;
138
139	reg [tx_rx_state_width - 1:0] tx_rx_state ;
140	reg [tx_rx_state_width - 1:0] tx_rx_next_state ;
141	reg tx_rx_sm_idle ;
142
143	reg scl_oe ;
144	reg scl_oe_en ;
145	reg sda_oe ;
146	reg sda_oe_en ;
147
148	reg sda_i_reg_en ;
149	reg sda_i_reg ;
150
151	always@(posedge clk_i or posedge reset_i)
152	begin
153	if (reset_i)
154	begin
155	clk_gen_cnt <= 'h0 ;
156
157	tx_rx_state <= tx_rx_idle ;
158
159	`ifdef ACTIVE_LOW_OE
160	pci_spoci_sda_oe_o <= 1'b1 ;
161	pci_spoci_scl_oe_o <= 1'b1 ;
162	`endif
163
164	`ifdef ACTIVE_HIGH_OE
165	pci_spoci_sda_oe_o <= 1'b0 ;
166	pci_spoci_scl_oe_o <= 1'b0 ;
167	`endif
168
169	sda_i_reg <= 1'b1 ;
170	end
171	else
172	begin
173	tx_rx_state <= tx_rx_next_state ;
174
175	if (clk_gen_cnt_clr)
176	clk_gen_cnt <= 'h0 ;
177	else if (clk_gen_cnt_en)
178	clk_gen_cnt <= clk_gen_cnt + 1'b1 ;
179
180
181	if (sda_oe_en)
182	begin
183	`ifdef ACTIVE_LOW_OE
184	pci_spoci_sda_oe_o <= ~sda_oe ;
185	`endif
186
187	`ifdef ACTIVE_HIGH_OE
188	pci_spoci_sda_oe_o <= sda_oe ;
189	`endif
190	end
191
192	if (scl_oe_en)
193	begin
194	`ifdef ACTIVE_LOW_OE
195	pci_spoci_scl_oe_o <= ~scl_oe ;
196	`endif
197
198	`ifdef ACTIVE_HIGH_OE
199	pci_spoci_scl_oe_o <= scl_oe ;
200	`endif
201	end
202
203	if (sda_i_reg_en)
204	sda_i_reg <= pci_spoci_sda_i ;
205	end
206	end
207
208	reg [ 7: 0] tx_shift_reg ;
209
210	reg send_start ;
211	reg start_sent ;
212
213	reg send_bit ;
214	reg bit_sent ;
215
216	reg rec_bit ;
217	reg bit_rec ;
218
219	reg rec_ack ;
220	reg ack_rec ;
221	reg nack_rec ;
222
223	reg send_ack ;
224	reg ack_sent ;
225	reg send_nack ;
226	reg nack_sent ;
227
228	reg send_stop ;
229	reg stop_sent ;
230
231	always@
232	(
233	tx_rx_state or
234	clk_gen_cnt or
235	send_start or
236	send_bit or
237	tx_shift_reg or
238	send_stop or
239	rec_ack or
240	sda_i_reg or
241	rec_bit or
242	send_ack or
243	send_nack
244	)
245	begin
246	clk_gen_cnt_clr = 1'b0 ;
247	clk_gen_cnt_en = 1'b0 ;
248	tx_rx_next_state = tx_rx_state ;
249	tx_rx_sm_idle = 1'b0 ;
250	scl_oe = 1'b0 ;
251	sda_oe = 1'b0 ;
252	scl_oe_en = 1'b0 ;
253	sda_oe_en = 1'b0 ;
254	start_sent = 1'b0 ;
255	bit_sent = 1'b0 ;
256	ack_rec = 1'b0 ;
257	nack_rec = 1'b0 ;
258	sda_i_reg_en = 1'b0 ;
259	stop_sent = 1'b0 ;
260	bit_rec = 1'b0 ;
261	ack_sent = 1'b0 ;
262	nack_sent = 1'b0 ;
263
264	case (tx_rx_state)
265
266	tx_rx_idle:
267	begin
268	tx_rx_sm_idle = 1'b1 ;
269
270	// from idle state, the only transition can be to the send start bit
271	if (send_start)
272	begin
273	tx_rx_next_state = tx_rx_start ;
274	clk_gen_cnt_clr = 1'b1 ;
275	end
276	end
277
278	tx_rx_start:
279	begin
280	clk_gen_cnt_en = 1'b1 ;
281	sda_oe = 1'b1 ;
282
283	// start bit is sent by transmiting 0 on the sda line
284	if (clk_gen_cnt == (period_cnt >> 1))
285	begin
286	start_sent = 1'b1 ;
287	sda_oe_en = 1'b1 ;
288	end
289
290	// after half clock period of driving the sda low, the only possible
291	// transition is to send state.
292	// if send bit is not active, stop the procedure - undrive sda
293	if (clk_gen_cnt == period_cnt)
294	begin
295	clk_gen_cnt_clr = 1'b1 ;
296	if (send_bit)
297	begin
298	tx_rx_next_state = tx_rx_send_bits ;
299	end
300	else
301	begin
302	sda_oe = 1'b0 ;
303	sda_oe_en = 1'b1 ;
304	tx_rx_next_state = tx_rx_idle ;
305	end
306	end
307	end
308
309	tx_rx_send_bits:
310	begin
311	clk_gen_cnt_en = 1'b1 ;
312
313	// generate high to low transition on the scl line immediately
314	if (clk_gen_cnt == 'h0)
315	begin
316	scl_oe = 1'b1 ;
317	scl_oe_en = 1'b1 ;
318	end
319
320	// after half of clock low time, load new value for sda oe, depending on the
321	// msb bit in the shift register
322	if (clk_gen_cnt == (period_cnt >> 2))
323	begin
324	sda_oe = ~tx_shift_reg[7] ;
325	sda_oe_en = 1'b1 ;
326	bit_sent = 1'b1 ;
327	end
328
329	// after clock low time, generate low to high transition on the scl line
330	if (clk_gen_cnt == (period_cnt >> 1))
331	begin
332	scl_oe = 1'b0 ;
333	scl_oe_en = 1'b1 ;
334	end
335
336	// after clock high time, check what to do next
337	if (clk_gen_cnt == (period_cnt))
338	begin
339	clk_gen_cnt_clr = 1'b1 ;
340
341	if (~send_bit)
342	begin
343	// after transmiting all the bits, the only possible transition is to the state
344	// that checks the eprom acknowledge
345	if (rec_ack)
346	tx_rx_next_state = tx_rx_rec_ack ;
347	else
348	begin
349	sda_oe = 1'b0 ;
350	sda_oe_en = 1'b1 ;
351	tx_rx_next_state = tx_rx_idle ;
352	end
353	end
354	end
355	end
356
357	tx_rx_rec_bits:
358	begin
359	clk_gen_cnt_en = 1'b1 ;
360	sda_i_reg_en = 1'b1 ;
361
362	// generate high to low transition on the scl line immediately
363	if (clk_gen_cnt == 'h0)
364	begin
365	scl_oe = 1'b1 ;
366	scl_oe_en = 1'b1 ;
367	end
368
369	// after half of clock low time, disable sda driver
370	if (clk_gen_cnt == (period_cnt >> 2))
371	begin
372	sda_oe = 1'b0 ;
373	sda_oe_en = 1'b1 ;
374	end
375
376	// after clock low time, generate low to high transition on the scl line
377	if (clk_gen_cnt == (period_cnt >> 1))
378	begin
379	scl_oe = 1'b0 ;
380	scl_oe_en = 1'b1 ;
381	end
382
383	// after half of clock high time, report received bit
384	if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
385	begin
386	bit_rec = 1'b1 ;
387	end
388
389	// after clock period is finished, check the next operation
390	if (clk_gen_cnt == (period_cnt))
391	begin
392	clk_gen_cnt_clr = 1'b1 ;
393
394	if (~rec_bit)
395	begin
396	// when all bits are received, only nack or ack next states are possible
397	if (send_ack)
398	tx_rx_next_state = tx_rx_send_ack ;
399	else if (send_nack)
400	tx_rx_next_state = tx_rx_send_nack ;
401	else
402	begin
403	tx_rx_next_state = tx_rx_idle ;
404	end
405	end
406	end
407	end
408
409	tx_rx_send_ack:
410	begin
411	clk_gen_cnt_en = 1'b1 ;
412
413	// generate high to low transition on the scl line
414	if (clk_gen_cnt == 'h0)
415	begin
416	scl_oe = 1'b1 ;
417	scl_oe_en = 1'b1 ;
418	end
419
420	// after half of clock low time, enable the sda driver
421	if (clk_gen_cnt == (period_cnt >> 2))
422	begin
423	sda_oe = 1'b1 ;
424	sda_oe_en = 1'b1 ;
425	ack_sent = 1'b1 ;
426	end
427
428	// after clock low time, disable the scl driver - generate low to high transition on the scl line
429	if (clk_gen_cnt == (period_cnt >> 1))
430	begin
431	scl_oe = 1'b0 ;
432	scl_oe_en = 1'b1 ;
433	end
434
435	// after clock period time expires, check what to do next
436	if (clk_gen_cnt == period_cnt)
437	begin
438	clk_gen_cnt_clr = 1'b1 ;
439
440	// after the byte is acknowledged, the only possible next state is receive bits
441	// state
442	if (rec_bit)
443	tx_rx_next_state = tx_rx_rec_bits ;
444	else
445	begin
446	// this should never happen
447	sda_oe = 1'b0 ;
448	sda_oe_en = 1'b1 ;
449
450	tx_rx_next_state = tx_rx_idle ;
451	end
452	end
453	end
454
455	tx_rx_rec_ack:
456	begin
457
458	clk_gen_cnt_en = 1'b1 ;
459	sda_i_reg_en = 1'b1 ;
460
461	// generate high to low transition on the scl line
462	if (clk_gen_cnt == 'h0)
463	begin
464	scl_oe = 1'b1 ;
465	scl_oe_en = 1'b1 ;
466	end
467
468	// after half of clock low time, disable the sda driver
469	if (clk_gen_cnt == (period_cnt >> 2))
470	begin
471	sda_oe = 1'b0 ;
472	sda_oe_en = 1'b1 ;
473	end
474
475	// after clock low time, disable the scl driver - generate low to high transition on the scl line
476	if (clk_gen_cnt == (period_cnt >> 1))
477	begin
478	scl_oe = 1'b0 ;
479	scl_oe_en = 1'b1 ;
480	end
481
482	// after 1/2 clock high time, report ack or nack condition, depending on the sda input state
483	if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
484	begin
485	ack_rec = ~sda_i_reg ;
486	nack_rec = sda_i_reg ;
487	end
488
489	// after clock period time expires, check what to do next
490	if (clk_gen_cnt == period_cnt)
491	begin
492	clk_gen_cnt_clr = 1'b1 ;
493
494	if (send_bit)
495	tx_rx_next_state = tx_rx_send_bits ;
496	else if (rec_bit)
497	tx_rx_next_state = tx_rx_rec_bits ;
498	else if (send_stop)
499	tx_rx_next_state = tx_rx_stop ;
500	else if (send_start)
501	tx_rx_next_state = tx_rx_restart ;
502	else
503	begin
504	// this should never happen
505	tx_rx_next_state = tx_rx_idle ;
506	end
507	end
508	end
509
510	tx_rx_send_nack:
511	begin
512	clk_gen_cnt_en = 1'b1 ;
513
514	// generate high to low transition on the scl line
515	if (clk_gen_cnt == 'h0)
516	begin
517	scl_oe = 1'b1 ;
518	scl_oe_en = 1'b1 ;
519	end
520
521	// after half of clock low time, disable the sda driver
522	if (clk_gen_cnt == (period_cnt >> 2))
523	begin
524	sda_oe = 1'b0 ;
525	sda_oe_en = 1'b1 ;
526	nack_sent = 1'b1 ;
527	end
528
529	// after clock low time, disable the scl driver - generate low to high transition on the scl line
530	if (clk_gen_cnt == (period_cnt >> 1))
531	begin
532	scl_oe = 1'b0 ;
533	scl_oe_en = 1'b1 ;
534	end
535
536	// after clock period time expires, check what to do next
537	if (clk_gen_cnt == period_cnt)
538	begin
539	clk_gen_cnt_clr = 1'b1 ;
540
541	// after the no acknowledge is sent, the only possible next state is stop
542	// state
543	if (send_stop)
544	tx_rx_next_state = tx_rx_stop ;
545	else
546	begin
547	// this should never happen
548	tx_rx_next_state = tx_rx_idle ;
549	end
550	end
551	end
552
553	tx_rx_restart:
554	begin
555	clk_gen_cnt_en = 1'b1 ;
556
557	// generate high to low transition
558	if (clk_gen_cnt == 'h0)
559	begin
560	scl_oe = 1'b1 ;
561	scl_oe_en = 1'b1 ;
562	end
563
564	// after half of clock low time, release sda line
565	if (clk_gen_cnt == (period_cnt >> 2))
566	begin
567	sda_oe = 1'b0 ;
568	sda_oe_en = 1'b1 ;
569	end
570
571	// generate low to high transition
572	if (clk_gen_cnt == (period_cnt >> 1))
573	begin
574	clk_gen_cnt_clr = 1'b1 ;
575
576	scl_oe = 1'b0 ;
577	scl_oe_en = 1'b1 ;
578
579	if (send_start)
580	tx_rx_next_state = tx_rx_start ;
581	else
582	tx_rx_next_state = tx_rx_idle ;
583	end
584	end
585
586	tx_rx_stop:
587	begin
588	clk_gen_cnt_en = 1'b1 ;
589
590	// generate high to low transition
591	if (clk_gen_cnt == 'h0)
592	begin
593	scl_oe = 1'b1 ;
594	scl_oe_en = 1'b1 ;
595	end
596
597	// after half of clock low time, drive sda line low
598	if (clk_gen_cnt == (period_cnt >> 2))
599	begin
600	sda_oe = 1'b1 ;
601	sda_oe_en = 1'b1 ;
602	end
603
604	// generate low to high transition
605	if (clk_gen_cnt == (period_cnt >> 1))
606	begin
607	scl_oe = 1'b0 ;
608	scl_oe_en = 1'b1 ;
609	end
610
611	// after full clock period, release the sda line
612	if (clk_gen_cnt == period_cnt)
613	begin
614	sda_oe = 1'b0 ;
615	sda_oe_en = 1'b1 ;
616	stop_sent = 1'b1 ;
617
618	tx_rx_next_state = tx_rx_idle ;
619	end
620	end
621
622	endcase
623	end
624
625	reg [rw_seq_state_width - 1:0] rw_seq_state ;
626
627	reg doing_read ,
628	doing_write ,
629	doing_seq_read ,
630	adr_set ;
631
632	reg [ 3: 0] bits_transfered ;
633
634	always@(posedge clk_i or posedge reset_i)
635	begin
636	if (reset_i)
637	begin
638	rw_seq_state <= rw_seq_idle ;
639	adr_set <= 1'b0 ;
640	doing_read <= 1'b0 ;
641	doing_write <= 1'b0 ;
642	doing_seq_read <= 1'b0 ;
643	dat_o <= 'h0 ;
644	tx_shift_reg <= 'h0 ;
645	send_start <= 'h0 ;
646	send_stop <= 'h0 ;
647	send_bit <= 'h0 ;
648	send_nack <= 'h0 ;
649	rec_ack <= 'h0 ;
650	no_ack_o <= 'h0 ;
651	bits_transfered <= 'h0 ;
652	write_done_o <= 'h0 ;
653	dat_rdy_o <= 'h0 ;
654	send_ack <= 'h0 ;
655	rec_bit <= 'h0 ;
656	end
657	else
658	begin
659
660	case (rw_seq_state)
661
662	rw_seq_idle:
663	begin
664	tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ;
665	adr_set <= 1'b0 ;
666
667	if ( tx_rx_sm_idle & ~(doing_write \| doing_read \| doing_seq_read) )
668	begin
669	if (do_write_i \| do_rnd_read_i \| do_seq_read_i)
670	begin
671	rw_seq_state <= rw_seq_tx_ctrl ;
672	send_start <= 1'b1 ;
673	end
674
675	if (do_write_i)
676	doing_write <= 1'b1 ;
677	else if (do_rnd_read_i)
678	doing_read <= 1'b1 ;
679	else if (do_seq_read_i)
680	doing_seq_read <= 1'b1 ;
681	end
682	else
683	begin
684	doing_write <= 1'b0 ;
685	doing_read <= 1'b0 ;
686	doing_seq_read <= 1'b0 ;
687	end
688	end
689
690	rw_seq_tx_ctrl:
691	begin
692	if (send_start)
693	begin
694	bits_transfered <= 'h0 ;
695
696	if (start_sent)
697	begin
698	send_start <= 1'b0 ;
699	send_bit <= 1'b1 ;
700	end
701	end
702	else if (send_bit)
703	begin
704	if (bit_sent)
705	begin
706	bits_transfered <= bits_transfered + 1'b1 ;
707	tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
708	end
709
710	if (bits_transfered == 'h8)
711	begin
712	send_bit <= 1'b0 ;
713	rec_ack <= 1'b1 ;
714	end
715	end
716	else if (rec_ack)
717	begin
718	bits_transfered <= 'h0 ;
719
720	if (ack_rec \| nack_rec)
721	rec_ack <= 1'b0 ;
722
723	if (ack_rec)
724	begin
725	if (doing_write \| ~adr_set)
726	begin
727	rw_seq_state <= rw_seq_tx_adr ;
728	tx_shift_reg <= adr_i[ 7: 0] ;
729	send_bit <= 1'b1 ;
730	end
731	else
732	begin
733	rw_seq_state <= rw_seq_rx_byte ;
734	rec_bit <= 1'b1 ;
735	end
736	end
737	else if (nack_rec)
738	begin
739	no_ack_o <= 1'b1 ;
740	send_stop <= 1'b1 ;
741	end
742	end
743	else if (send_stop)
744	begin
745	no_ack_o <= 1'b0 ;
746
747	if (stop_sent)
748	begin
749	send_stop <= 1'b0 ;
750	rw_seq_state <= rw_seq_idle ;
751	end
752	end
753	end
754
755	rw_seq_tx_adr:
756	begin
757	if (send_bit)
758	begin
759	if (bit_sent)
760	begin
761	bits_transfered <= bits_transfered + 1'b1 ;
762	tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
763	end
764
765	if (bits_transfered == 'h8)
766	begin
767	send_bit <= 1'b0 ;
768	rec_ack <= 1'b1 ;
769	end
770	end
771	else if (rec_ack)
772	begin
773	bits_transfered <= 'h0 ;
774
775	if (ack_rec \| nack_rec)
776	rec_ack <= 1'b0 ;
777
778	if (ack_rec)
779	begin
780
781	adr_set <= 1'b1 ;
782
783	if (doing_write)
784	begin
785	send_bit <= 1'b1 ;
786	rw_seq_state <= rw_seq_tx_byte ;
787	tx_shift_reg <= dat_i ;
788	end
789	else if (doing_read \| doing_seq_read)
790	begin
791	send_start <= 1'b1 ;
792	rw_seq_state <= rw_seq_tx_ctrl ;
793	tx_shift_reg <= 8'b10100001 ;
794	end
795	end
796	else if (nack_rec)
797	begin
798	no_ack_o <= 1'b1 ;
799	send_stop <= 1'b1 ;
800	end
801	end
802	else if (send_stop)
803	begin
804	no_ack_o <= 1'b0 ;
805
806	if (stop_sent)
807	begin
808	send_stop <= 1'b0 ;
809	rw_seq_state <= rw_seq_idle ;
810	end
811	end
812	end
813
814	rw_seq_tx_byte:
815	begin
816	if (send_bit)
817	begin
818	if (bit_sent)
819	begin
820	bits_transfered <= bits_transfered + 1'b1 ;
821	tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
822	end
823
824	if (bits_transfered == 'h8)
825	begin
826	send_bit <= 1'b0 ;
827	rec_ack <= 1'b1 ;
828	end
829	end
830	else if (rec_ack)
831	begin
832	bits_transfered <= 'h0 ;
833
834	if (ack_rec \| nack_rec)
835	begin
836	rec_ack <= 1'b0 ;
837	send_stop <= 1'b1 ;
838	end
839
840	if (nack_rec)
841	no_ack_o <= 1'b1 ;
842
843	if (ack_rec)
844	write_done_o <= 1'b1 ;
845	end
846	else if (send_stop)
847	begin
848	no_ack_o <= 1'b0 ;
849	write_done_o <= 1'b0 ;
850
851	if (stop_sent)
852	begin
853	send_stop <= 1'b0 ;
854	rw_seq_state <= rw_seq_idle ;
855	end
856	end
857	end
858
859	rw_seq_rx_byte:
860	begin
861	if (rec_bit)
862	begin
863	if (bit_rec)
864	begin
865	bits_transfered <= bits_transfered + 1'b1 ;
866	dat_o <= {dat_o[6:0], sda_i_reg} ;
867	end
868
869	if (bits_transfered == 'h8)
870	begin
871	rec_bit <= 1'b0 ;
872	dat_rdy_o <= 1'b1 ;
873	if (doing_read)
874	send_nack <= 1'b1 ;
875	else
876	send_ack <= 1'b1 ;
877	end
878	end
879	else if (send_nack)
880	begin
881	dat_rdy_o <= 1'b0 ;
882	bits_transfered <= 'h0 ;
883
884	if (nack_sent)
885	begin
886	send_stop <= 1'b1 ;
887	send_nack <= 1'b0 ;
888	end
889	end
890	else if (send_ack)
891	begin
892	dat_rdy_o <= 1'b0 ;
893	bits_transfered <= 'h0 ;
894
895	if (~do_seq_read_i)
896	begin
897	send_ack <= 1'b0 ;
898	send_nack <= 1'b1 ;
899	end
900	else if (ack_sent)
901	begin
902	send_ack <= 1'b0 ;
903	rec_bit <= 1'b1 ;
904	end
905	end
906	else if (send_stop)
907	begin
908	if (stop_sent)
909	begin
910	send_stop <= 1'b0 ;
911	rw_seq_state <= rw_seq_idle ;
912	end
913	end
914	end
915	endcase
916	end
917	end
918
919	endmodule // pci_spoci_ctrl