dos2unix *.vhd

[raggedstone] / dhwk / source / INTERRUPT.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: INTERRUPT.VHD

library ieee;
use ieee.std_logic_1164.all;

entity INTERRUPT is
	port
	(
	PCI_CLOCK		:in		std_logic;
	PCI_RSTn		:in 	std_logic; -- PCI reset is asynchron (low active)
	RESET				:in 	std_logic;
	TAST_SETn		:in 	std_logic;
	TAST_RESn		:in 	std_logic;
	INT_IN_0		:in		std_logic;
	INT_IN_1		:in		std_logic;
	INT_IN_2		:in		std_logic;
	INT_IN_3		:in		std_logic;
	INT_IN_4		:in		std_logic;
	INT_IN_5		:in		std_logic;
	INT_IN_6		:in		std_logic;
	INT_IN_7		:in		std_logic;
	TRDYn				:in 	std_logic;  -- event 1 after read of Interrupt status register (low active)
	READ_XX5_4	:in 	std_logic;	-- event 2 after read of Interrupt status register
	INT_RES			:in		std_logic_vector(7 downto 0); -- clear selected interrupts
	INT_MASKE		:in		std_logic_vector(7 downto 0);	-- interrupt mask register
	INT_REG			:out	std_logic_vector(7 downto 0); -- interrupt status register
	INTAn				:out	std_logic;	-- second interrupt line for PCI analyzer
	PCI_INTAn		:out	std_logic		-- PCI interrupt line 
	);

end entity INTERRUPT;

architecture INTERRUPT_DESIGN of INTERRUPT is

	signal	SIG_TAST_Q		:std_logic;
	signal	SIG_TAST_Qn		:std_logic;


	signal	SIG_INTA			:std_logic; 

	signal FF_A			:std_logic_vector(7 downto 0);
	signal FF_B			:std_logic_vector(7 downto 0);	
	signal SET 			:std_logic_vector(7 downto 0);	

	signal  SIG_PROPAGATE_INT :std_logic;
	signal  SIG_PROPAGATE_INT_SECOND :std_logic;
	signal  REG :std_logic_vector(7 downto 0);

begin




------------------------------------------------------
	process (PCI_CLOCK) 
	begin 
		if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  

                        -- THIS IS BROKEN (it cycles the interrupt)
			SIG_TAST_Q		<= not (TAST_SETn and SIG_TAST_Qn);
			SIG_TAST_Qn		<= not (TAST_RESn and SIG_TAST_Q);
	
		end if;
	end process; 	

------------------------------------------------------

	process (PCI_CLOCK)
	begin
    if (PCI_RSTn = '0') then
					SET <= "00000000";
          FF_A	<= "00000000";
          FF_B	<= "00000000";

		elsif(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then
   		if(RESET = '1') then
						SET <= "00000000";
            FF_A	<= "00000000";
            FF_B	<= "00000000";
      else	

			FF_A(0)	<=			INT_IN_0 ;  -- Receive FIFO Empty Flag

			FF_A(1)	<=			INT_IN_1 ;  -- Send FIFO Half Full
			FF_A(2)	<=			INT_IN_2 ; 
			FF_A(3)	<=			INT_IN_3 ; 

			FF_A(4)	<=			INT_IN_4 ; 

			FF_A(5)	<=			INT_IN_5 ; 
			FF_A(6)	<=			INT_IN_6 ; 
			FF_A(7)	<=			INT_IN_7 ; 

			FF_B	<= FF_A ;

			SET <= FF_A AND not FF_B;
		end if;
		end if;
	end process;

	process (PCI_CLOCK,PCI_RSTn)
	begin
		if (PCI_RSTn = '0') then
			REG <= "00000000";

		elsif(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then
				if(RESET = '1') then
					REG <= "00000000";

    		-- elsif(SIG_TAST_Q = '1') then
      		-- 	REG <= "00000000" or SET;
		

        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
            REG <= (REG AND NOT INT_RES) OR SET;
        else
            REG <= REG OR SET;
        end if;
    end if;
	end process;

	SIG_PROPAGATE_INT <=
            (REG(0) AND INT_MASKE(0)) 
            OR (REG(1) AND INT_MASKE(1))
            OR (REG(2) AND INT_MASKE(2))
            OR (REG(3) AND INT_MASKE(3))
            OR (REG(4) AND INT_MASKE(4))
            OR (REG(5) AND INT_MASKE(5))
            OR (REG(6) AND INT_MASKE(6))
            OR (REG(7) AND INT_MASKE(7));

	process (PCI_CLOCK)
	begin
		if(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then
   	SIG_PROPAGATE_INT_SECOND	<= not SIG_PROPAGATE_INT;
    end if;
  end process;


   	  INTAn	<= not SIG_PROPAGATE_INT_SECOND;
    	PCI_INTAn	<= '0'	when SIG_PROPAGATE_INT_SECOND = '0'	else	'Z';

	INT_REG <= REG;

end architecture INTERRUPT_DESIGN;