[raggedstone] / dhwk / source / config_space_header.vhd

-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity CONFIG_SPACE_HEADER is
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             ADDR_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             CF_RD_COM : In    std_logic;
             CF_WR_COM : In    std_logic;
             IRDY_REGn : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
                PERR : In    std_logic;
             REVISION_ID : In    std_logic_vector (7 downto 0);
                SERR : In    std_logic;
               TRDYn : In    std_logic;
             VENDOR_ID : In    std_logic_vector (15 downto 0);
             CONF_DATA : Out   std_logic_vector (31 downto 0);
             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);
             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
end CONFIG_SPACE_HEADER;

architecture SCHEMATIC of CONFIG_SPACE_HEADER is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal CONF_WR_04H : std_logic;
   signal CONF_WR_10H : std_logic;
   signal CONF_WR_3CH : std_logic;
   signal CONF_READ_SEL : std_logic_vector (2 downto 0);
   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
   signal CONF_DATA_08H : std_logic_vector (31 downto 0);
   signal CONF_DATA_00H : std_logic_vector (31 downto 0);

   component CONFIG_MUX_0
      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);
             CONF_DATA_04H : In    std_logic_vector (31 downto 0);
             CONF_DATA_08H : In    std_logic_vector (31 downto 0);
             CONF_DATA_10H : In    std_logic_vector (31 downto 0);
             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);
             READ_SEL : In    std_logic_vector (2 downto 0);
             CONF_DATA : Out   std_logic_vector (31 downto 0) );
   end component;

   component CONFIG_RD_0
      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
             CF_RD_COM : In    std_logic;
             READ_SEL : Out   std_logic_vector (2 downto 0) );
   end component;

   component CONFIG_WR_0
      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
             CF_WR_COM : In    std_logic;
             IRDY_REGn : In    std_logic;
               TRDYn : In    std_logic;
             CONF_WR_04H : Out   std_logic;
             CONF_WR_10H : Out   std_logic;
             CONF_WR_3CH : Out   std_logic );
   end component;

   component CONFIG_3CH
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             CONF_WR_3CH : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );
   end component;

   component CONFIG_10H
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             CONF_WR_10H : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
   end component;

   component CONFIG_08H
      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);
             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );
   end component;

   component CONFIG_00H
      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);
             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );
   end component;

   component CONFIG_04H
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             CONF_WR_04H : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
                PERR : In    std_logic;
                SERR : In    std_logic;
             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );
   end component;

begin

   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;

   I10 : CONFIG_MUX_0
      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
   I9 : CONFIG_RD_0
      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                 CF_RD_COM=>CF_RD_COM,
                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
   I8 : CONFIG_WR_0
      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
   I6 : CONFIG_3CH
      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
                 PCI_RSTn=>PCI_RSTn,
                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
   I5 : CONFIG_10H
      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
                 PCI_RSTn=>PCI_RSTn,
                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
   I4 : CONFIG_08H
      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
   I3 : CONFIG_00H
      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
   I2 : CONFIG_04H
      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );

end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
	2
	3
	4
	5	LIBRARY ieee;
	6
	7	USE ieee.std_logic_1164.ALL;
	8	USE ieee.numeric_std.ALL;
	9
	10
	11	entity CONFIG_SPACE_HEADER is
	12	Port ( AD_REG : In std_logic_vector (31 downto 0);
	13	ADDR_REG : In std_logic_vector (31 downto 0);
	14	CBE_REGn : In std_logic_vector (3 downto 0);
	15	CF_RD_COM : In std_logic;
	16	CF_WR_COM : In std_logic;
	17	IRDY_REGn : In std_logic;
	18	PCI_CLOCK : In std_logic;
	19	PCI_RSTn : In std_logic;
	20	PERR : In std_logic;
	21	REVISION_ID : In std_logic_vector (7 downto 0);
	22	SERR : In std_logic;
	23	TRDYn : In std_logic;
	24	VENDOR_ID : In std_logic_vector (15 downto 0);
	25	CONF_DATA : Out std_logic_vector (31 downto 0);
	26	CONF_DATA_04H : Out std_logic_vector (31 downto 0);
	27	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
	28	end CONFIG_SPACE_HEADER;
	29
	30	architecture SCHEMATIC of CONFIG_SPACE_HEADER is
	31
	32	SIGNAL gnd : std_logic := '0';
	33	SIGNAL vcc : std_logic := '1';
	34
	35	signal CONF_WR_04H : std_logic;
	36	signal CONF_WR_10H : std_logic;
	37	signal CONF_WR_3CH : std_logic;
	38	signal CONF_READ_SEL : std_logic_vector (2 downto 0);
	39	signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
	40	signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
	41	signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
	42	signal CONF_DATA_08H : std_logic_vector (31 downto 0);
	43	signal CONF_DATA_00H : std_logic_vector (31 downto 0);
	44
	45	component CONFIG_MUX_0
	46	Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
	47	CONF_DATA_04H : In std_logic_vector (31 downto 0);
	48	CONF_DATA_08H : In std_logic_vector (31 downto 0);
	49	CONF_DATA_10H : In std_logic_vector (31 downto 0);
	50	CONF_DATA_3CH : In std_logic_vector (31 downto 0);
	51	READ_SEL : In std_logic_vector (2 downto 0);
	52	CONF_DATA : Out std_logic_vector (31 downto 0) );
	53	end component;
	54
	55	component CONFIG_RD_0
	56	Port ( ADDR_REG : In std_logic_vector (31 downto 0);
	57	CF_RD_COM : In std_logic;
	58	READ_SEL : Out std_logic_vector (2 downto 0) );
	59	end component;
	60
	61	component CONFIG_WR_0
	62	Port ( ADDR_REG : In std_logic_vector (31 downto 0);
	63	CF_WR_COM : In std_logic;
	64	IRDY_REGn : In std_logic;
65	TRDYn : In std_logic;
66	CONF_WR_04H : Out std_logic;
67	CONF_WR_10H : Out std_logic;
68	CONF_WR_3CH : Out std_logic );
69	end component;
70
71	component CONFIG_3CH
72	Port ( AD_REG : In std_logic_vector (31 downto 0);
73	CBE_REGn : In std_logic_vector (3 downto 0);
74	CONF_WR_3CH : In std_logic;
75	PCI_CLOCK : In std_logic;
76	PCI_RSTn : In std_logic;
77	CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
78	end component;
79
80	component CONFIG_10H
81	Port ( AD_REG : In std_logic_vector (31 downto 0);
82	CBE_REGn : In std_logic_vector (3 downto 0);
83	CONF_WR_10H : In std_logic;
84	PCI_CLOCK : In std_logic;
85	PCI_RSTn : In std_logic;
86	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
87	end component;
88
89	component CONFIG_08H
90	Port ( REVISION_ID : In std_logic_vector (7 downto 0);
91	CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
92	end component;
93
94	component CONFIG_00H
95	Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
96	CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
97	end component;
98
99	component CONFIG_04H
100	Port ( AD_REG : In std_logic_vector (31 downto 0);
101	CBE_REGn : In std_logic_vector (3 downto 0);
102	CONF_WR_04H : In std_logic;
103	PCI_CLOCK : In std_logic;
104	PCI_RSTn : In std_logic;
105	PERR : In std_logic;
106	SERR : In std_logic;
107	CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
108	end component;
109
110	begin
111
112	CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
113	CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
114
115	I10 : CONFIG_MUX_0
116	Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
117	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
118	CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
119	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
120	CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
121	READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
122	CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
123	I9 : CONFIG_RD_0
124	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
125	CF_RD_COM=>CF_RD_COM,
126	READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
127	I8 : CONFIG_WR_0
128	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
129	CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
130	TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
131	CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
132	I6 : CONFIG_3CH
133	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
134	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
135	CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
136	PCI_RSTn=>PCI_RSTn,
137	CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
138	I5 : CONFIG_10H
139	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
140	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
141	CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
142	PCI_RSTn=>PCI_RSTn,
143	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
144	I4 : CONFIG_08H
145	Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
146	CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
147	I3 : CONFIG_00H
148	Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
149	CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
150	I2 : CONFIG_04H
151	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
152	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
153	CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
154	PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
155	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
156
157	end SCHEMATIC;