dos2unix *.vhd

[raggedstone] / dhwk / source / vergleich.vhd

-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity VERGLEICH is
      Port (    IN_A : In    std_logic_vector (31 downto 0);
                IN_B : In    std_logic_vector (31 downto 0);
             GLEICH_OUT : Out   std_logic );
end VERGLEICH;

architecture SCHEMATIC of VERGLEICH is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal   GLEICH : std_logic_vector (7 downto 0);

   component VERG_2
      Port (    IN_A : In    std_logic_vector (1 downto 0);
                IN_B : In    std_logic_vector (1 downto 0);
              GLEICH : Out   std_logic );
   end component;

   component VERG_8
      Port (  GLEICH : In    std_logic_vector (7 downto 0);
             GLEICH_OUT : Out   std_logic );
   end component;

   component VERG_4
      Port (    IN_A : In    std_logic_vector (3 downto 0);
                IN_B : In    std_logic_vector (3 downto 0);
              GLEICH : Out   std_logic );
   end component;

begin

   I11 : VERG_2
      Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
                 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
   I9 : VERG_8
      Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
                 GLEICH_OUT=>GLEICH_OUT );
   I8 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
                 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
   I7 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
                 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
   I6 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
                 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
   I5 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
                 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
   I4 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
                 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
   I3 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
                 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
   I2 : VERG_4
      Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
                 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );

end SCHEMATIC;