[raggedstone] / dhwk / source / pci_interface.vhd

-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity PCI_INTERFACE is
      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);
             PCI_CLOCK : In    std_logic;
             PCI_FRAMEn : In    std_logic;
             PCI_IDSEL : In    std_logic;
             PCI_IRDYn : In    std_logic;
             PCI_RSTn : In    std_logic;
             READ_FIFO : In    std_logic;
             REVISON_ID : In    std_logic_vector (7 downto 0);
             USER_DATA_OUT : In    std_logic_vector (31 downto 0);
             VENDOR_ID : In    std_logic_vector (15 downto 0);
              PCI_AD : InOut std_logic_vector (31 downto 0);
             PCI_PAR : InOut std_logic;
              AD_REG : Out   std_logic_vector (31 downto 0);
             ADDR_REG : Out   std_logic_vector (31 downto 0);
             CBE_REGn : Out   std_logic_vector (3 downto 0);
             DEVSELn : Out   std_logic;
             FIFO_RDn : Out   std_logic;
             IO_WR_COM : Out   std_logic;
             IRDY_REGn : Out   std_logic;
             PCI_DEVSELn : Out   std_logic;
             PCI_PERRn : Out   std_logic;
             PCI_SERRn : Out   std_logic;
             PCI_STOPn : Out   std_logic;
             PCI_TRDYn : Out   std_logic;
             READ_SEL : Out   std_logic_vector (1 downto 0);
               TRDYn : Out   std_logic );
end PCI_INTERFACE;

architecture SCHEMATIC of PCI_INTERFACE is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal IRDY_REGn_DUMMY : std_logic;
   signal  PAR_REG : std_logic;
   signal     PERR : std_logic;
   signal     SERR : std_logic;
   signal CF_RD_COM : std_logic;
   signal CF_WR_COM : std_logic;
   signal      LAR : std_logic;
   signal  MY_ADDR : std_logic;
   signal SERR_CHECK : std_logic;
   signal IDSEL_REG : std_logic;
   signal FRAME_REGn : std_logic;
   signal PERR_CHECK : std_logic;
   signal OE_PCI_PAR : std_logic;
   signal OE_PCI_PERR : std_logic;
   signal TRDYn_DUMMY : std_logic;
   signal CONF_DATA_10H : std_logic_vector (31 downto 0);
   signal CONF_DATA_04H : std_logic_vector (31 downto 0);
   signal CONF_DATA : std_logic_vector (31 downto 0);
   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
   signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
   signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);

   component STEUERUNG
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             FRAME_REGn : In    std_logic;
             IDSEL_REG : In    std_logic;
             IO_SPACE : In    std_logic;
             MY_ADDR : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
             READ_FIFO : In    std_logic;
             CF_RD_COM : Out   std_logic;
             CF_WR_COM : Out   std_logic;
             DEVSELn : Out   std_logic;
             FIFO_RDn : Out   std_logic;
             IO_RD_COM : Out   std_logic;
             IO_WR_COM : Out   std_logic;
                 LAR : Out   std_logic;
             OE_PCI_PAR : Out   std_logic;
             OE_PCI_PERR : Out   std_logic;
             PCI_DEVSELn : Out   std_logic;
             PCI_STOPn : Out   std_logic;
             PCI_TRDYn : Out   std_logic;
             PERR_CHECK : Out   std_logic;
                READ : Out   std_logic;
             SERR_CHECK : Out   std_logic;
               TRDYn : Out   std_logic );
   end component;

   component PARITY
      Port ( OE_PCI_PAR : In    std_logic;
             OE_PCI_PERR : In    std_logic;
             PA_ER_RE : In    std_logic;
              PAR_IN : In    std_logic_vector (35 downto 0);
             PAR_REG : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
             PERR_CHECK : In    std_logic;
             SERR_CHECK : In    std_logic;
             SERR_ENA : In    std_logic;
             PCI_PAR : InOut std_logic;
             PCI_PERRn : Out   std_logic;
             PCI_SERRn : Out   std_logic;
                PERR : Out   std_logic;
                SERR : Out   std_logic );
   end component;

   component VERGLEICH
      Port (    IN_A : In    std_logic_vector (31 downto 0);
                IN_B : In    std_logic_vector (31 downto 0);
             GLEICH_OUT : Out   std_logic );
   end component;

   component IO_MUX_REG
      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);
             LOAD_ADDR_REG : In    std_logic;
             PCI_CBEn : In    std_logic_vector (3 downto 0);
             PCI_CLOCK : In    std_logic;
             PCI_FRAMEn : In    std_logic;
             PCI_IDSEL : In    std_logic;
             PCI_IRDYn : In    std_logic;
             PCI_PAR : In    std_logic;
             PCI_RSTn : In    std_logic;
             READ_SEL : In    std_logic_vector (1 downto 0);
             USER_DATA : In    std_logic_vector (31 downto 0);
              PCI_AD : InOut std_logic_vector (31 downto 0);
              AD_REG : Out   std_logic_vector (31 downto 0);
             ADDR_REG : Out   std_logic_vector (31 downto 0);
             CBE_REGn : Out   std_logic_vector (3 downto 0);
             FRAME_REGn : Out   std_logic;
             IDSEL_REG : Out   std_logic;
             IRDY_REGn : Out   std_logic;
             PAR_REG : Out   std_logic );
   end component;

   component CONFIG_SPACE_HEADER
      Port (  AD_REG : In    std_logic_vector (31 downto 0);
             ADDR_REG : In    std_logic_vector (31 downto 0);
             CBE_REGn : In    std_logic_vector (3 downto 0);
             CF_RD_COM : In    std_logic;
             CF_WR_COM : In    std_logic;
             IRDY_REGn : In    std_logic;
             PCI_CLOCK : In    std_logic;
             PCI_RSTn : In    std_logic;
                PERR : In    std_logic;
             REVISION_ID : In    std_logic_vector (7 downto 0);
                SERR : In    std_logic;
               TRDYn : In    std_logic;
             VENDOR_ID : In    std_logic_vector (15 downto 0);
             CONF_DATA : Out   std_logic_vector (31 downto 0);
             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);
             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
   end component;

begin

   ADDR_REG <= ADDR_REG_DUMMY;
   AD_REG <= AD_REG_DUMMY;
   CBE_REGn <= CBE_REGn_DUMMY;
   READ_SEL <= READ_SEL_DUMMY;
   TRDYn <= TRDYn_DUMMY;
   IRDY_REGn <= IRDY_REGn_DUMMY;

   I7 : STEUERUNG
      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
                 IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
                 READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
                 CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
                 FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
                 IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
                 PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
                 SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
   I5 : PARITY
      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
                 PA_ER_RE=>CONF_DATA_04H(6),
                 PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                 PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
                 PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
                 SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
                 PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
                 PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
   I4 : VERGLEICH
      Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
                 IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                 GLEICH_OUT=>MY_ADDR );
   I2 : IO_MUX_REG
      Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                 LOAD_ADDR_REG=>LAR,
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
                 USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
                 IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
   I1 : CONFIG_SPACE_HEADER
      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
                 CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
                 IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
                 PCI_RSTn=>PCI_RSTn, PERR=>PERR,
                 REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
                 SERR=>SERR, TRDYn=>TRDYn_DUMMY,
                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );

end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007
	2
	3
	4
	5	LIBRARY ieee;
	6
	7	USE ieee.std_logic_1164.ALL;
	8	USE ieee.numeric_std.ALL;
	9
	10
	11	entity PCI_INTERFACE is
	12	Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
	13	PCI_CLOCK : In std_logic;
	14	PCI_FRAMEn : In std_logic;
	15	PCI_IDSEL : In std_logic;
	16	PCI_IRDYn : In std_logic;
	17	PCI_RSTn : In std_logic;
	18	READ_FIFO : In std_logic;
	19	REVISON_ID : In std_logic_vector (7 downto 0);
	20	USER_DATA_OUT : In std_logic_vector (31 downto 0);
	21	VENDOR_ID : In std_logic_vector (15 downto 0);
	22	PCI_AD : InOut std_logic_vector (31 downto 0);
	23	PCI_PAR : InOut std_logic;
	24	AD_REG : Out std_logic_vector (31 downto 0);
	25	ADDR_REG : Out std_logic_vector (31 downto 0);
	26	CBE_REGn : Out std_logic_vector (3 downto 0);
	27	DEVSELn : Out std_logic;
	28	FIFO_RDn : Out std_logic;
	29	IO_WR_COM : Out std_logic;
	30	IRDY_REGn : Out std_logic;
	31	PCI_DEVSELn : Out std_logic;
	32	PCI_PERRn : Out std_logic;
	33	PCI_SERRn : Out std_logic;
	34	PCI_STOPn : Out std_logic;
	35	PCI_TRDYn : Out std_logic;
	36	READ_SEL : Out std_logic_vector (1 downto 0);
	37	TRDYn : Out std_logic );
	38	end PCI_INTERFACE;
	39
	40	architecture SCHEMATIC of PCI_INTERFACE is
	41
	42	SIGNAL gnd : std_logic := '0';
	43	SIGNAL vcc : std_logic := '1';
	44
	45	signal IRDY_REGn_DUMMY : std_logic;
	46	signal PAR_REG : std_logic;
	47	signal PERR : std_logic;
	48	signal SERR : std_logic;
	49	signal CF_RD_COM : std_logic;
	50	signal CF_WR_COM : std_logic;
	51	signal LAR : std_logic;
	52	signal MY_ADDR : std_logic;
	53	signal SERR_CHECK : std_logic;
	54	signal IDSEL_REG : std_logic;
	55	signal FRAME_REGn : std_logic;
	56	signal PERR_CHECK : std_logic;
	57	signal OE_PCI_PAR : std_logic;
	58	signal OE_PCI_PERR : std_logic;
	59	signal TRDYn_DUMMY : std_logic;
	60	signal CONF_DATA_10H : std_logic_vector (31 downto 0);
	61	signal CONF_DATA_04H : std_logic_vector (31 downto 0);
	62	signal CONF_DATA : std_logic_vector (31 downto 0);
	63	signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
	64	signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
65	signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
66	signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
67
68	component STEUERUNG
69	Port ( AD_REG : In std_logic_vector (31 downto 0);
70	CBE_REGn : In std_logic_vector (3 downto 0);
71	FRAME_REGn : In std_logic;
72	IDSEL_REG : In std_logic;
73	IO_SPACE : In std_logic;
74	MY_ADDR : In std_logic;
75	PCI_CLOCK : In std_logic;
76	PCI_RSTn : In std_logic;
77	READ_FIFO : In std_logic;
78	CF_RD_COM : Out std_logic;
79	CF_WR_COM : Out std_logic;
80	DEVSELn : Out std_logic;
81	FIFO_RDn : Out std_logic;
82	IO_RD_COM : Out std_logic;
83	IO_WR_COM : Out std_logic;
84	LAR : Out std_logic;
85	OE_PCI_PAR : Out std_logic;
86	OE_PCI_PERR : Out std_logic;
87	PCI_DEVSELn : Out std_logic;
88	PCI_STOPn : Out std_logic;
89	PCI_TRDYn : Out std_logic;
90	PERR_CHECK : Out std_logic;
91	READ : Out std_logic;
92	SERR_CHECK : Out std_logic;
93	TRDYn : Out std_logic );
94	end component;
95
96	component PARITY
97	Port ( OE_PCI_PAR : In std_logic;
98	OE_PCI_PERR : In std_logic;
99	PA_ER_RE : In std_logic;
100	PAR_IN : In std_logic_vector (35 downto 0);
101	PAR_REG : In std_logic;
102	PCI_CLOCK : In std_logic;
103	PCI_RSTn : In std_logic;
104	PERR_CHECK : In std_logic;
105	SERR_CHECK : In std_logic;
106	SERR_ENA : In std_logic;
107	PCI_PAR : InOut std_logic;
108	PCI_PERRn : Out std_logic;
109	PCI_SERRn : Out std_logic;
110	PERR : Out std_logic;
111	SERR : Out std_logic );
112	end component;
113
114	component VERGLEICH
115	Port ( IN_A : In std_logic_vector (31 downto 0);
116	IN_B : In std_logic_vector (31 downto 0);
117	GLEICH_OUT : Out std_logic );
118	end component;
119
120	component IO_MUX_REG
121	Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
122	LOAD_ADDR_REG : In std_logic;
123	PCI_CBEn : In std_logic_vector (3 downto 0);
124	PCI_CLOCK : In std_logic;
125	PCI_FRAMEn : In std_logic;
126	PCI_IDSEL : In std_logic;
127	PCI_IRDYn : In std_logic;
128	PCI_PAR : In std_logic;
129	PCI_RSTn : In std_logic;
130	READ_SEL : In std_logic_vector (1 downto 0);
131	USER_DATA : In std_logic_vector (31 downto 0);
132	PCI_AD : InOut std_logic_vector (31 downto 0);
133	AD_REG : Out std_logic_vector (31 downto 0);
134	ADDR_REG : Out std_logic_vector (31 downto 0);
135	CBE_REGn : Out std_logic_vector (3 downto 0);
136	FRAME_REGn : Out std_logic;
137	IDSEL_REG : Out std_logic;
138	IRDY_REGn : Out std_logic;
139	PAR_REG : Out std_logic );
140	end component;
141
142	component CONFIG_SPACE_HEADER
143	Port ( AD_REG : In std_logic_vector (31 downto 0);
144	ADDR_REG : In std_logic_vector (31 downto 0);
145	CBE_REGn : In std_logic_vector (3 downto 0);
146	CF_RD_COM : In std_logic;
147	CF_WR_COM : In std_logic;
148	IRDY_REGn : In std_logic;
149	PCI_CLOCK : In std_logic;
150	PCI_RSTn : In std_logic;
151	PERR : In std_logic;
152	REVISION_ID : In std_logic_vector (7 downto 0);
153	SERR : In std_logic;
154	TRDYn : In std_logic;
155	VENDOR_ID : In std_logic_vector (15 downto 0);
156	CONF_DATA : Out std_logic_vector (31 downto 0);
157	CONF_DATA_04H : Out std_logic_vector (31 downto 0);
158	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
159	end component;
160
161	begin
162
163	ADDR_REG <= ADDR_REG_DUMMY;
164	AD_REG <= AD_REG_DUMMY;
165	CBE_REGn <= CBE_REGn_DUMMY;
166	READ_SEL <= READ_SEL_DUMMY;
167	TRDYn <= TRDYn_DUMMY;
168	IRDY_REGn <= IRDY_REGn_DUMMY;
169
170	I7 : STEUERUNG
171	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
172	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
173	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
174	IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
175	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
176	READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
177	CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
178	FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
179	IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
180	OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
181	PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
182	PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
183	SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
184	I5 : PARITY
185	Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
186	PA_ER_RE=>CONF_DATA_04H(6),
187	PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
188	PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
189	PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
190	PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
191	SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
192	PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
193	PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
194	I4 : VERGLEICH
195	Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
196	IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
197	GLEICH_OUT=>MY_ADDR );
198	I2 : IO_MUX_REG
199	Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
200	LOAD_ADDR_REG=>LAR,
201	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
202	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
203	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
204	PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
205	READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
206	USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
207	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
208	AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
209	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
210	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
211	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
212	IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
213	I1 : CONFIG_SPACE_HEADER
214	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
215	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
216	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
217	CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
218	IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
219	PCI_RSTn=>PCI_RSTn, PERR=>PERR,
220	REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
221	SERR=>SERR, TRDYn=>TRDYn_DUMMY,
222	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
223	CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
224	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
225	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
226
227	end SCHEMATIC;