[raggedstone] / dhwk / source / verg_8.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: VERG_8.VHD

library ieee;
use ieee.std_logic_1164.all;

entity VERG_8 is
	port
	(
	GLEICH			:in		std_logic_vector(7 downto 0);
	GLEICH_OUT	:out	std_logic
	);

end entity VERG_8 ;

architecture VERG_8_DESIGN of VERG_8 is
 

begin

--	GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte

--	GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 0)	=	"11111111"	else	'0';    
		GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 1)	=	"1111111"		else	'0'; 
 
end architecture VERG_8_DESIGN ;
Commit	Line	Data
696ded12	1	-- J.STELZNER
	2	-- INFORMATIK-3 LABOR
	3	-- 23.08.2006
	4	-- File: VERG_8.VHD
	5
	6	library ieee;
	7	use ieee.std_logic_1164.all;
	8
	9	entity VERG_8 is
	10	port
	11	(
	12	GLEICH :in std_logic_vector(7 downto 0);
	13	GLEICH_OUT :out std_logic
	14	);
	15
	16	end entity VERG_8 ;
	17
	18	architecture VERG_8_DESIGN of VERG_8 is
	19
	20
	21	begin
	22
	23	-- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
	24
	25	-- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
	26	GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
	27
	28	end architecture VERG_8_DESIGN ;