more LA signals

[raggedstone] / dhwk / source / REG.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: REG.VHD\r
\r
library ieee ;\r
use ieee.std_logic_1164.all ;\r
\r
entity REG is\r
	port\r
	(\r
	CLOCK		:in		std_logic; \r
	RESET		:in		std_logic; \r
	WRITE		:in		std_logic;   \r
	REG_IN	:in		std_logic_vector(7 downto 0);\r
	REG_OUT	:out	std_logic_vector(7 downto 0) \r
	);\r
end entity REG ;\r
\r
architecture REG_DESIGN of REG is\r
\r
	signal SIG_REG	:std_logic_vector (7 downto 0);\r
\r
begin\r
\r
	process (CLOCK) \r
	begin\r
		if (CLOCK'event and CLOCK = '1') then\r
			if			RESET	=	'1'	then	SIG_REG	<= X"00";\r
				elsif	WRITE	=	'1'	then	SIG_REG	<= REG_IN;\r
 				else										SIG_REG	<= SIG_REG;\r
  		end if;\r
		end if;\r
	end process;\r
\r
	REG_OUT <= SIG_REG;\r
\r
end architecture REG_DESIGN;\r