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377c0242 1-----------------------------------------------------------------------------\r
2-- --\r
3-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --\r
4-- --\r
5-- This source file may be used and distributed without restriction --\r
6-- provided that this copyright statement is not removed from the file --\r
7-- and that any derivative work contains this copyright notice. --\r
8-- --\r
9-- Primitive library for post synthesis simulation --\r
10-- These models are not intended for efficient synthesis --\r
11-- --\r
12-----------------------------------------------------------------------------\r
13library ieee;\r
14use ieee.std_logic_1164.all;\r
15entity prim_counter is\r
16 generic (w : integer := 8);\r
17 port (\r
18 q : buffer std_logic_vector(w - 1 downto 0);\r
19 cout : out std_logic;\r
20 d : in std_logic_vector(w - 1 downto 0);\r
21 cin : in std_logic;\r
22 clk : in std_logic;\r
23 rst : in std_logic;\r
24 load : in std_logic;\r
25 en : in std_logic;\r
26 updn : in std_logic\r
27 );\r
28end prim_counter;\r
29\r
30architecture beh of prim_counter is\r
31 signal nextq : std_logic_vector(w - 1 downto 0);\r
32begin\r
33 nxt: process (q, cin, updn)\r
34 variable i : integer;\r
35 variable nextc, c : std_logic;\r
36 begin\r
37 nextc := cin;\r
38 for i in 0 to w - 1 loop\r
39 c := nextc;\r
40 nextq(i) <= c xor (not updn) xor q(i);\r
41 nextc := (c and (not updn)) or \r
42 (c and q(i)) or\r
43 ((not updn) and q(i));\r
44 end loop;\r
45 cout <= nextc;\r
46 end process;\r
47\r
48 ff : process (clk, rst)\r
49 begin\r
50 if rst = '1' then\r
51 q <= (others => '0');\r
52 elsif rising_edge(clk) then\r
53 q <= nextq;\r
54 end if;\r
55 end process ff;\r
56end beh;\r
57\r
58library ieee;\r
59use ieee.std_logic_1164.all;\r
60entity prim_dff is\r
61 port (q : out std_logic;\r
62 d : in std_logic;\r
63 clk : in std_logic;\r
64 r : in std_logic := '0';\r
65 s : in std_logic := '0');\r
66end prim_dff;\r
67\r
68architecture beh of prim_dff is\r
69begin\r
70 ff : process (clk, r, s)\r
71 begin\r
72 if r = '1' then\r
73 q <= '0';\r
74 elsif s = '1' then\r
75 q <= '1';\r
76 elsif rising_edge(clk) then\r
77 q <= d;\r
78 end if;\r
79 end process ff;\r
80end beh;\r
81\r
82library ieee;\r
83use ieee.std_logic_1164.all;\r
84entity prim_latch is\r
85 port (q : out std_logic;\r
86 d : in std_logic;\r
87 clk : in std_logic;\r
88 r : in std_logic := '0';\r
89 s : in std_logic := '0');\r
90end prim_latch;\r
91\r
92architecture beh of prim_latch is\r
93begin\r
94 q <= '0' when r = '1' else\r
95 '1' when s = '1' else\r
96 d when clk = '1';\r
97end beh;\r
98\r
99\r
100library ieee;\r
101use ieee.std_logic_1164.all;\r
102use ieee.std_logic_unsigned.all;\r
103\r
104entity prim_ramd is\r
105generic (\r
106 data_width : integer := 4;\r
107 addr_width : integer := 5);\r
108port (\r
109 dout : out std_logic_vector(data_width-1 downto 0);\r
110 aout : in std_logic_vector(addr_width-1 downto 0);\r
111 din : in std_logic_vector(data_width-1 downto 0);\r
112 ain : in std_logic_vector(addr_width-1 downto 0);\r
113 we : in std_logic;\r
114 clk : in std_logic);\r
115end prim_ramd;\r
116\r
117architecture beh of prim_ramd is\r
118\r
119constant depth : integer := 2** addr_width;\r
120type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);\r
121signal mem: mem_type;\r
122\r
123begin \r
124\r
125dout <= mem(conv_integer(aout));\r
126\r
127process (clk)\r
128 begin\r
129 if rising_edge(clk) then \r
130 if (we = '1') then\r
131 mem(conv_integer(ain)) <= din;\r
132 end if;\r
133 end if;\r
134end process;\r
135\r
136end beh ;\r
137\r
138\r
139library ieee;\r
140use ieee.std_logic_1164.all;\r
141package components is\r
142 component prim_counter\r
143 generic (w : integer);\r
144 port (\r
145 q : buffer std_logic_vector(w - 1 downto 0);\r
146 cout : out std_logic;\r
147 d : in std_logic_vector(w - 1 downto 0);\r
148 cin : in std_logic;\r
149 clk : in std_logic;\r
150 rst : in std_logic;\r
151 load : in std_logic;\r
152 en : in std_logic;\r
153 updn : in std_logic\r
154 );\r
155 end component;\r
156 component prim_dff\r
157 port (q : out std_logic;\r
158 d : in std_logic;\r
159 clk : in std_logic;\r
160 r : in std_logic := '0';\r
161 s : in std_logic := '0');\r
162 end component;\r
163 component prim_latch\r
164 port (q : out std_logic;\r
165 d : in std_logic;\r
166 clk : in std_logic;\r
167 r : in std_logic := '0';\r
168 s : in std_logic := '0');\r
169 end component;\r
170\r
171 component prim_ramd is\r
172 generic (\r
173 data_width : integer := 4;\r
174 addr_width : integer := 5);\r
175 port (\r
176 dout : out std_logic_vector(data_width-1 downto 0);\r
177 aout : in std_logic_vector(addr_width-1 downto 0);\r
178 din : in std_logic_vector(data_width-1 downto 0);\r
179 ain : in std_logic_vector(addr_width-1 downto 0);\r
180 we : in std_logic;\r
181 clk : in std_logic);\r
182 end component;\r
183\r
184end components;\r
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