this file is no longer autogenerated

[raggedstone] / dhwk / source / pci / steuerung.vhd

-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

entity STEUERUNG is
        Port (  AD_REG : In    std_logic_vector (31 downto 0);
                CBE_REGn : In    std_logic_vector (3 downto 0);
                FRAME_REGn : In    std_logic;
                IDSEL_REG : In    std_logic;
                IO_SPACE : In    std_logic;
                MY_ADDR : In    std_logic;
                PCI_CLOCK : In    std_logic;
                PCI_RSTn : In    std_logic;
                READ_FIFO : In    std_logic;
                CF_RD_COM : Out   std_logic;
                CF_WR_COM : Out   std_logic;
                DEVSELn : Out   std_logic;
                FIFO_RDn : Out   std_logic;
                IO_RD_COM : Out   std_logic;
                IO_WR_COM : Out   std_logic;
                LAR : Out   std_logic;
                OE_PCI_PAR : Out   std_logic;
                OE_PCI_PERR : Out   std_logic;
                PCI_DEVSELn : Out   std_logic;
                PCI_STOPn : Out   std_logic;
                PCI_TRDYn : Out   std_logic;
                PERR_CHECK : Out   std_logic;
                READ : Out   std_logic;
                SERR_CHECK : Out   std_logic;
                TRDYn : Out   std_logic );
end STEUERUNG;

architecture SCHEMATIC of STEUERUNG is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal DEVSELn_DUMMY : std_logic;
        signal  IO_READ : std_logic;
        signal IO_WRITE : std_logic;
        signal CONF_READ : std_logic;
        signal CONF_WRITE : std_logic;

        component CONT_FSM
                Port ( CONF_READ : In    std_logic;
                       CONF_WRITE : In    std_logic;
                       FIFO_READ : In    std_logic;
                       IO_READ : In    std_logic;
                       IO_WRITE : In    std_logic;
                       PCI_CLOCK : In    std_logic;
                       PCI_RSTn : In    std_logic;
                       DEVSELn : Out   std_logic;
                       FIFO_RDn : Out   std_logic;
                       OE_PCI_PAR : Out   std_logic;
                       OE_PCI_PERR : Out   std_logic;
                       PCI_DEVSELn : Out   std_logic;
                       PCI_STOPn : Out   std_logic;
                       PCI_TRDYn : Out   std_logic;
                       PERR_CHECK : Out   std_logic;
                       READ : Out   std_logic;
                       TRDYn : Out   std_logic );
        end component;

        component COMM_FSM
                Port ( CONF_READ : In    std_logic;
                       CONF_WRITE : In    std_logic;
                       DEVSELn : In    std_logic;
                       IO_READ : In    std_logic;
                       IO_WRITE : In    std_logic;
                       PCI_CLOCK : In    std_logic;
                       PCI_RSTn : In    std_logic;
                       CF_RD_COM : Out   std_logic;
                       CF_WR_COM : Out   std_logic;
                       IO_RD_COM : Out   std_logic;
                       IO_WR_COM : Out   std_logic );
        end component;

        component COMM_DEC
                Port (  AD_REG : In    std_logic_vector (31 downto 0);
                        CBE_REGn : In    std_logic_vector (3 downto 0);
                        FRAME_REGn : In    std_logic;
                        IDSEL_REG : In    std_logic;
                        IO_SPACE : In    std_logic;
                        MY_ADDR : In    std_logic;
                        PCI_CLOCK : In    std_logic;
                        PCI_RSTn : In    std_logic;
                        CONF_READ : Out   std_logic;
                        CONF_WRITE : Out   std_logic;
                        IO_READ : Out   std_logic;
                        IO_WRITE : Out   std_logic;
                        LAR : Out   std_logic;
                        SERR_CHECK : Out   std_logic );
        end component;

begin

        DEVSELn <= DEVSELn_DUMMY;

        I1 : CONT_FSM
        Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
                   FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
                   IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
                   PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
                   FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
                   OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
                   PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
                   PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
        I2 : COMM_FSM
        Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
                   DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
                   IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
                   PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
                   CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
                   IO_WR_COM=>IO_WR_COM );
        I3 : COMM_DEC
        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
        FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
        IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
        PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
        CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
        IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
        SERR_CHECK=>SERR_CHECK );

end SCHEMATIC;