[raggedstone] / dhwk_old / source / generic_fifo_sc_a.v

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Universal FIFO Single Clock                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  D/L from: http://www.opencores.org/cores/generic_fifos/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: generic_fifo_sc_a.v,v 1.2 2007-02-11 22:21:28 michael Exp $
//
//  $Date: 2007-02-11 22:21:28 $
//  $Revision: 1.2 $
//  $Author: michael $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: generic_fifo_sc_a.v,v $
//               Revision 1.2  2007-02-11 22:21:28  michael
//               fix address width
//
//               Revision 1.1  2007/02/11 21:58:30  sithglan
//               += fifo
//
//               Revision 1.1.1.1  2002/09/25 05:42:06  rudi
//               Initial Checkin
//
//
//
//
//
//
//
//
//
//
//

`include "timescale.v"

/*

Description
===========

I/Os
----
rst	low active, either sync. or async. master reset (see below how to select)
clr	synchronous clear (just like reset but always synchronous), high active
re	read enable, synchronous, high active
we	read enable, synchronous, high active
din	Data Input
dout	Data Output

full	Indicates the FIFO is full (combinatorial output)
full_r	same as above, but registered output (see note below)
empty	Indicates the FIFO is empty
empty_r	same as above, but registered output (see note below)

full_n		Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r	same as above, but registered output (see note below)
empty_n		Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r	same as above, but registered output (see note below)

level		indicates the FIFO level:
		2'b00	0-25%	 full
		2'b01	25-50%	 full
		2'b10	50-75%	 full
		2'b11	%75-100% full

combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).

Parameters
----------
The FIFO takes 3 parameters:
dw	Data bus width
aw	Address bus width (Determines the FIFO size by evaluating 2^aw)
n	N is a second status threshold constant for full_n and empty_n
	If you have no need for the second status threshold, do not
	connect the outputs and the logic should be removed by your
	synthesis tool.

Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.


Misc
----
This design assumes you will do appropriate status checking externally.

IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.

*/


// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset

`define SC_FIFO_ASYNC_RESET				// Uncomment for Syncr. reset
//`define SC_FIFO_ASYNC_RESET	or negedge rst		// Uncomment for Async. reset


module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
			full, empty, full_r, empty_r,
			full_n, empty_n, full_n_r, empty_n_r,
			level);

parameter dw=8;
parameter aw=12;
parameter n=32;
parameter max_size = 1<<aw;

input			clk, rst, clr;
input	[dw-1:0]	din;
input			we;
output	[dw-1:0]	dout;
input			re;
output			full, full_r;
output			empty, empty_r;
output			full_n, full_n_r;
output			empty_n, empty_n_r;
output	[1:0]		level;

////////////////////////////////////////////////////////////////////
//
// Local Wires
//

reg	[aw-1:0]	wp;
wire	[aw-1:0]	wp_pl1;
wire	[aw-1:0]	wp_pl2;
reg	[aw-1:0]	rp;
wire	[aw-1:0]	rp_pl1;
reg			full_r;
reg			empty_r;
reg			gb;
reg			gb2;
reg	[aw:0]		cnt;
wire			full_n, empty_n;
reg			full_n_r, empty_n_r;

////////////////////////////////////////////////////////////////////
//
// Memory Block
//

generic_dpram  #(aw,dw) u0(
	.rclk(		clk		),
	.rrst(		!rst		),
	.rce(		1'b1		),
	.oe(		1'b1		),
	.raddr(		rp		),
	.do(		dout		),
	.wclk(		clk		),
	.wrst(		!rst		),
	.wce(		1'b1		),
	.we(		we		),
	.waddr(		wp		),
	.di(		din		)
	);

////////////////////////////////////////////////////////////////////
//
// Misc Logic
//

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	wp <= #1 {aw{1'b0}};
	else
	if(clr)		wp <= #1 {aw{1'b0}};
	else
	if(we)		wp <= #1 wp_pl1;

assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	rp <= #1 {aw{1'b0}};
	else
	if(clr)		rp <= #1 {aw{1'b0}};
	else
	if(re)		rp <= #1 rp_pl1;

assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};

////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//

assign empty = ((wp == rp) & !gb);
assign full  = ((wp == rp) &  gb);

// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)			gb <= #1 1'b0;
	else
	if(clr)				gb <= #1 1'b0;
	else
	if((wp_pl1 == rp) & we)		gb <= #1 1'b1;
	else
	if(re)				gb <= #1 1'b0;

////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//

// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)			gb2 <= #1 1'b0;
	else
	if(clr)				gb2 <= #1 1'b0;
	else
	if((wp_pl2 == rp) & we)		gb2 <= #1 1'b1;
	else
	if((wp != rp) & re)		gb2 <= #1 1'b0;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				full_r <= #1 1'b0;
	else
	if(clr)					full_r <= #1 1'b0;
	else
	if(we & ((wp_pl1 == rp) & gb2) & !re)	full_r <= #1 1'b1;
	else
	if(re & ((wp_pl1 != rp) | !gb2) & !we)	full_r <= #1 1'b0;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				empty_r <= #1 1'b1;
	else
	if(clr)					empty_r <= #1 1'b1;
	else
	if(we & ((wp != rp_pl1) | gb2) & !re)	empty_r <= #1 1'b0;
	else
	if(re & ((wp == rp_pl1) & !gb2) & !we)	empty_r <= #1 1'b1;

////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n & Empty_n Flags
//

assign empty_n = cnt < n;
assign full_n  = !(cnt < (max_size-n+1));
assign level = {2{cnt[aw]}} | cnt[aw-1:aw-2];

// N entries status
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	cnt <= #1 {aw+1{1'b0}};
	else
	if(clr)		cnt <= #1 {aw+1{1'b0}};
	else
	if( re & !we)	cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
	else
	if(!re &  we)	cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};

////////////////////////////////////////////////////////////////////
//
// Registered Full_n & Empty_n Flags
//

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				empty_n_r <= #1 1'b1;
	else
	if(clr)					empty_n_r <= #1 1'b1;
	else
	if(we & (cnt >= (n-1) ) & !re)		empty_n_r <= #1 1'b0;
	else
	if(re & (cnt <= n ) & !we)		empty_n_r <= #1 1'b1;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				full_n_r <= #1 1'b0;
	else
	if(clr)					full_n_r <= #1 1'b0;
	else
	if(we & (cnt >= (max_size-n) ) & !re)	full_n_r <= #1 1'b1;
	else
	if(re & (cnt <= (max_size-n+1)) & !we)	full_n_r <= #1 1'b0;

////////////////////////////////////////////////////////////////////
//
// Sanity Check
//

// synopsys translate_off
always @(posedge clk)
	if(we & full)
		$display("%m WARNING: Writing while fifo is FULL (%t)",$time);

always @(posedge clk)
	if(re & empty)
		$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
// synopsys translate_on

endmodule
Commit	Line	Data
96e85c4d	1	/////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// Universal FIFO Single Clock ////
	4	//// ////
	5	//// ////
	6	//// Author: Rudolf Usselmann ////
	7	//// rudi@asics.ws ////
	8	//// ////
	9	//// ////
	10	//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
	11	//// ////
	12	/////////////////////////////////////////////////////////////////////
	13	//// ////
	14	//// Copyright (C) 2000-2002 Rudolf Usselmann ////
	15	//// www.asics.ws ////
	16	//// rudi@asics.ws ////
	17	//// ////
	18	//// This source file may be used and distributed without ////
	19	//// restriction provided that this copyright statement is not ////
	20	//// removed from the file and that any derivative work contains ////
	21	//// the original copyright notice and the associated disclaimer.////
	22	//// ////
	23	//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
	24	//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
	25	//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
	26	//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
	27	//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
	28	//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
	29	//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
	30	//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
	31	//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
	32	//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
	33	//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
	34	//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
	35	//// POSSIBILITY OF SUCH DAMAGE. ////
	36	//// ////
	37	/////////////////////////////////////////////////////////////////////
	38
	39	// CVS Log
	40	//
31301d44	41	// $Id: generic_fifo_sc_a.v,v 1.2 2007-02-11 22:21:28 michael Exp $
96e85c4d	42	//
31301d44	43	// $Date: 2007-02-11 22:21:28 $
	44	// $Revision: 1.2 $
	45	// $Author: michael $
96e85c4d	46	// $Locker: $
	47	// $State: Exp $
	48	//
	49	// Change History:
	50	// $Log: generic_fifo_sc_a.v,v $
31301d44	51	// Revision 1.2 2007-02-11 22:21:28 michael
	52	// fix address width
	53	//
	54	// Revision 1.1 2007/02/11 21:58:30 sithglan
96e85c4d	55	// += fifo
	56	//
	57	// Revision 1.1.1.1 2002/09/25 05:42:06 rudi
	58	// Initial Checkin
	59	//
	60	//
	61	//
	62	//
	63	//
	64	//
	65	//
	66	//
	67	//
	68	//
	69	//
	70
	71	`include "timescale.v"
	72
	73	/*
	74
	75	Description
	76	===========
	77
	78	I/Os
	79	----
	80	rst low active, either sync. or async. master reset (see below how to select)
	81	clr synchronous clear (just like reset but always synchronous), high active
	82	re read enable, synchronous, high active
	83	we read enable, synchronous, high active
	84	din Data Input
	85	dout Data Output
	86
	87	full Indicates the FIFO is full (combinatorial output)
	88	full_r same as above, but registered output (see note below)
	89	empty Indicates the FIFO is empty
	90	empty_r same as above, but registered output (see note below)
	91
	92	full_n Indicates if the FIFO has space for N entries (combinatorial output)
	93	full_n_r same as above, but registered output (see note below)
	94	empty_n Indicates the FIFO has at least N entries (combinatorial output)
	95	empty_n_r same as above, but registered output (see note below)
	96
	97	level indicates the FIFO level:
	98	2'b00 0-25% full
	99	2'b01 25-50% full
	100	2'b10 50-75% full
	101	2'b11 %75-100% full
	102
	103	combinatorial vs. registered status outputs
	104	-------------------------------------------
	105	Both the combinatorial and registered status outputs have exactly the same
	106	synchronous timing. Meaning they are being asserted immediately at the clock
	107	edge after the last read or write. The combinatorial outputs however, pass
	108	through several levels of logic before they are output. The registered status
	109	outputs are direct outputs of a flip-flop. The reason both are provided, is
	110	that the registered outputs require quite a bit of additional logic inside
	111	the FIFO. If you can meet timing of your device with the combinatorial
	112	outputs, use them ! The FIFO will be smaller. If the status signals are
	113	in the critical pass, use the registered outputs, they have a much smaller
	114	output delay (actually only Tcq).
	115
	116	Parameters
	117	----------
	118	The FIFO takes 3 parameters:
119	dw Data bus width
120	aw Address bus width (Determines the FIFO size by evaluating 2^aw)
121	n N is a second status threshold constant for full_n and empty_n
122	If you have no need for the second status threshold, do not
123	connect the outputs and the logic should be removed by your
124	synthesis tool.
125
126	Synthesis Results
127	-----------------
128	In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
129	at about 116 MHz (IO insertion disabled). The registered status outputs
130	are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
131	available.
132
133
134	Misc
135	----
136	This design assumes you will do appropriate status checking externally.
137
138	IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
139	empty will place the FIFO in an undefined state.
140
141	*/
142
143
144	// Selecting Sync. or Async Reset
145	// ------------------------------
146	// Uncomment one of the two lines below. The first line for
147	// synchronous reset, the second for asynchronous reset
148
149	`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
150	//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
151
152
153	module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
154	full, empty, full_r, empty_r,
155	full_n, empty_n, full_n_r, empty_n_r,
156	level);
157
158	parameter dw=8;
31301d44	159	parameter aw=12;
96e85c4d	160	parameter n=32;
	161	parameter max_size = 1<<aw;
	162
	163	input clk, rst, clr;
	164	input [dw-1:0] din;
	165	input we;
	166	output [dw-1:0] dout;
	167	input re;
	168	output full, full_r;
	169	output empty, empty_r;
	170	output full_n, full_n_r;
	171	output empty_n, empty_n_r;
	172	output [1:0] level;
	173
	174	////////////////////////////////////////////////////////////////////
	175	//
	176	// Local Wires
	177	//
	178
	179	reg [aw-1:0] wp;
	180	wire [aw-1:0] wp_pl1;
	181	wire [aw-1:0] wp_pl2;
	182	reg [aw-1:0] rp;
	183	wire [aw-1:0] rp_pl1;
	184	reg full_r;
	185	reg empty_r;
	186	reg gb;
	187	reg gb2;
	188	reg [aw:0] cnt;
	189	wire full_n, empty_n;
	190	reg full_n_r, empty_n_r;
	191
	192	////////////////////////////////////////////////////////////////////
	193	//
	194	// Memory Block
	195	//
	196
	197	generic_dpram #(aw,dw) u0(
	198	.rclk( clk ),
	199	.rrst( !rst ),
	200	.rce( 1'b1 ),
	201	.oe( 1'b1 ),
	202	.raddr( rp ),
	203	.do( dout ),
	204	.wclk( clk ),
	205	.wrst( !rst ),
	206	.wce( 1'b1 ),
	207	.we( we ),
	208	.waddr( wp ),
	209	.di( din )
	210	);
	211
	212	////////////////////////////////////////////////////////////////////
	213	//
	214	// Misc Logic
	215	//
	216
	217	always @(posedge clk `SC_FIFO_ASYNC_RESET)
	218	if(!rst) wp <= #1 {aw{1'b0}};
	219	else
	220	if(clr) wp <= #1 {aw{1'b0}};
	221	else
	222	if(we) wp <= #1 wp_pl1;
	223
224	assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
225	assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};
226
227	always @(posedge clk `SC_FIFO_ASYNC_RESET)
228	if(!rst) rp <= #1 {aw{1'b0}};
229	else
230	if(clr) rp <= #1 {aw{1'b0}};
231	else
232	if(re) rp <= #1 rp_pl1;
233
234	assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};
235
236	////////////////////////////////////////////////////////////////////
237	//
238	// Combinatorial Full & Empty Flags
239	//
240
241	assign empty = ((wp == rp) & !gb);
242	assign full = ((wp == rp) & gb);
243
244	// Guard Bit ...
245	always @(posedge clk `SC_FIFO_ASYNC_RESET)
246	if(!rst) gb <= #1 1'b0;
247	else
248	if(clr) gb <= #1 1'b0;
249	else
250	if((wp_pl1 == rp) & we) gb <= #1 1'b1;
251	else
252	if(re) gb <= #1 1'b0;
253
254	////////////////////////////////////////////////////////////////////
255	//
256	// Registered Full & Empty Flags
257	//
258
259	// Guard Bit ...
260	always @(posedge clk `SC_FIFO_ASYNC_RESET)
261	if(!rst) gb2 <= #1 1'b0;
262	else
263	if(clr) gb2 <= #1 1'b0;
264	else
265	if((wp_pl2 == rp) & we) gb2 <= #1 1'b1;
266	else
267	if((wp != rp) & re) gb2 <= #1 1'b0;
268
269	always @(posedge clk `SC_FIFO_ASYNC_RESET)
270	if(!rst) full_r <= #1 1'b0;
271	else
272	if(clr) full_r <= #1 1'b0;
273	else
274	if(we & ((wp_pl1 == rp) & gb2) & !re) full_r <= #1 1'b1;
275	else
276	if(re & ((wp_pl1 != rp) \| !gb2) & !we) full_r <= #1 1'b0;
277
278	always @(posedge clk `SC_FIFO_ASYNC_RESET)
279	if(!rst) empty_r <= #1 1'b1;
280	else
281	if(clr) empty_r <= #1 1'b1;
282	else
283	if(we & ((wp != rp_pl1) \| gb2) & !re) empty_r <= #1 1'b0;
284	else
285	if(re & ((wp == rp_pl1) & !gb2) & !we) empty_r <= #1 1'b1;
286
287	////////////////////////////////////////////////////////////////////
288	//
289	// Combinatorial Full_n & Empty_n Flags
290	//
291
292	assign empty_n = cnt < n;
293	assign full_n = !(cnt < (max_size-n+1));
294	assign level = {2{cnt[aw]}} \| cnt[aw-1:aw-2];
295
296	// N entries status
297	always @(posedge clk `SC_FIFO_ASYNC_RESET)
298	if(!rst) cnt <= #1 {aw+1{1'b0}};
299	else
300	if(clr) cnt <= #1 {aw+1{1'b0}};
301	else
302	if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
303	else
304	if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};
305
306	////////////////////////////////////////////////////////////////////
307	//
308	// Registered Full_n & Empty_n Flags
309	//
310
311	always @(posedge clk `SC_FIFO_ASYNC_RESET)
312	if(!rst) empty_n_r <= #1 1'b1;
313	else
314	if(clr) empty_n_r <= #1 1'b1;
315	else
316	if(we & (cnt >= (n-1) ) & !re) empty_n_r <= #1 1'b0;
317	else
318	if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1;
319
320	always @(posedge clk `SC_FIFO_ASYNC_RESET)
321	if(!rst) full_n_r <= #1 1'b0;
322	else
323	if(clr) full_n_r <= #1 1'b0;
324	else
325	if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1;
326	else
327	if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0;
328
329	////////////////////////////////////////////////////////////////////
330	//
331	// Sanity Check
332	//
333
334	// synopsys translate_off
335	always @(posedge clk)
336	if(we & full)
337	$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
338
339	always @(posedge clk)
340	if(re & empty)
341	$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
342	// synopsys translate_on
343
344	endmodule
345