[raggedstone] / dhwk / source / PAR_SER_CON.vhd

-- $Id: PAR_SER_CON.vhd,v 1.2 2007-03-10 16:08:48 michael Exp $\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
use ieee.std_logic_unsigned.all;\r
\r
entity	PAR_SER_CON	is\r
	port\r
	(\r
	PCI_CLOCK		:in	std_logic; \r
	RESET				:in	std_logic; \r
	PSC_ENABLE			:in	std_logic; -- Parallel Serial Converter Enable\r
	SYNC_S_FIFO_EFn	                :in	std_logic; -- Empty Flag (low active)\r
	SPC_RDY_IN			:in	std_logic; -- Ready to receive data\r
 	PAR_IN				:in	std_logic_vector(7 downto 0);\r
	SER_OUT				:out	std_logic; -- Serial Output\r
	S_FIFO_READn		        :out	std_logic  -- FIFO Read (low active)\r
	);			\r
end entity	PAR_SER_CON ;\r
\r
architecture PAR_SER_CON_DESIGN	of PAR_SER_CON is\r
\r
constant STATE_END        :std_logic_vector(3 downto 0) := "0001";\r
constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";\r
constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
\r
signal COUNT     :std_logic_vector (3 downto 0);\r
signal STATE     :std_logic_vector (3 downto 0); \r
signal DATUM     :std_logic_vector (7 downto 0);\r
signal SYNC			 :std_logic; -- make SPC_RDY_IN stable\r
\r
attribute syn_state_machine:boolean;\r
attribute syn_state_machine of STATE: signal is false;\r
attribute syn_state_machine of COUNT: signal is false;\r
begin\r
\r
process(PCI_CLOCK)\r
begin\r
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
				        if ("0000" < COUNT) then\r
        				        COUNT <= COUNT - 1;\r
				        end if;\r
\r
                if (RESET = '1') then\r
                        STATE <= STATE_SEND;\r
                        COUNT <= "0000";\r
                        SER_OUT <= '0';\r
                        S_FIFO_READn <= '1';\r
\r
                elsif (PSC_ENABLE = '1') then\r
		if (COUNT = "0000") then\r
                        COUNT <= "0011";\r
                        case STATE is\r
                                when STATE_SEND =>\r
                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
                                                SER_OUT <= '1';\r
                                                S_FIFO_READn <= '0';\r
                                                STATE <= STATE_SEND_BIT_0;\r
                                        end if;\r
\r
                                when STATE_SEND_BIT_0 =>\r
                                                DATUM     <= PAR_IN;\r
                                                S_FIFO_READn <= '1';\r
                                                SER_OUT <= PAR_IN(0); \r
                                                STATE <= STATE_SEND_BIT_1;\r
                                  \r
                                when STATE_SEND_BIT_1 =>\r
                                        SER_OUT <= DATUM(1); \r
                                        STATE <= STATE_SEND_BIT_2;\r
\r
                                when STATE_SEND_BIT_2 =>\r
                                        SER_OUT <= DATUM(2); \r
                                        STATE <= STATE_SEND_BIT_3;\r
\r
                                when STATE_SEND_BIT_3 =>\r
                                        SER_OUT <= DATUM(3); \r
                                        STATE <= STATE_SEND_BIT_4;\r
\r
                                when STATE_SEND_BIT_4 =>\r
                                        SER_OUT <= DATUM(4); \r
                                        STATE <= STATE_SEND_BIT_5;\r
                                        \r
                                when STATE_SEND_BIT_5 =>\r
                                        SER_OUT <= DATUM(5); \r
                                        STATE <= STATE_SEND_BIT_6;\r
\r
                                when STATE_SEND_BIT_6 =>\r
                                        SER_OUT <= DATUM(6); \r
                                        STATE <= STATE_SEND_BIT_7;\r
                                        \r
                                when STATE_SEND_BIT_7 =>\r
                                        SER_OUT <= DATUM(7); \r
                                        STATE <= STATE_END;\r
\r
                                when STATE_END =>\r
                                        SER_OUT <= '0';\r
                                        STATE <= STATE_SEND;\r
\r
                                when others => STATE <= STATE_END;\r
                        end case;\r
		    else\r
		    	S_FIFO_READn <= '1';\r
                    end if; -- COUNT\r
                end if; -- RESET ... / PSC_ENABLE ...\r
        end if; -- PCI_CLOCK ...\r
end process;\r
\r
process(PCI_CLOCK)\r
begin\r
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
						SYNC <= SPC_RDY_IN;\r
				end if;\r
end process;\r
\r
\r
end architecture PAR_SER_CON_DESIGN;\r
Commit	Line	Data
097d51b9	1	-- $Id: PAR_SER_CON.vhd,v 1.2 2007-03-10 16:08:48 michael Exp $\r
377c0242	2	\r
	3	library ieee;\r
	4	use ieee.std_logic_1164.all;\r
	5	use ieee.std_logic_unsigned.all;\r
	6	\r
	7	entity PAR_SER_CON is\r
	8	port\r
	9	(\r
	10	PCI_CLOCK :in std_logic; \r
	11	RESET :in std_logic; \r
	12	PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable\r
	13	SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active)\r
	14	SPC_RDY_IN :in std_logic; -- Ready to receive data\r
	15	PAR_IN :in std_logic_vector(7 downto 0);\r
	16	SER_OUT :out std_logic; -- Serial Output\r
	17	S_FIFO_READn :out std_logic -- FIFO Read (low active)\r
	18	); \r
	19	end entity PAR_SER_CON ;\r
	20	\r
	21	architecture PAR_SER_CON_DESIGN of PAR_SER_CON is\r
	22	\r
	23	constant STATE_END :std_logic_vector(3 downto 0) := "0001";\r
	24	constant STATE_SEND :std_logic_vector(3 downto 0) := "0010";\r
	25	constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
	26	constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
	27	constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
	28	constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
	29	constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
	30	constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
	31	constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
	32	constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
	33	\r
	34	signal COUNT :std_logic_vector (3 downto 0);\r
	35	signal STATE :std_logic_vector (3 downto 0); \r
	36	signal DATUM :std_logic_vector (7 downto 0);\r
	37	signal SYNC :std_logic; -- make SPC_RDY_IN stable\r
	38	\r
	39	attribute syn_state_machine:boolean;\r
	40	attribute syn_state_machine of STATE: signal is false;\r
	41	attribute syn_state_machine of COUNT: signal is false;\r
	42	begin\r
	43	\r
	44	process(PCI_CLOCK)\r
	45	begin\r
	46	if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
	47	if ("0000" < COUNT) then\r
	48	COUNT <= COUNT - 1;\r
	49	end if;\r
	50	\r
	51	if (RESET = '1') then\r
	52	STATE <= STATE_SEND;\r
	53	COUNT <= "0000";\r
	54	SER_OUT <= '0';\r
	55	S_FIFO_READn <= '1';\r
	56	\r
	57	elsif (PSC_ENABLE = '1') then\r
097d51b9	58	if (COUNT = "0000") then\r
377c0242	59	COUNT <= "0011";\r
	60	case STATE is\r
	61	when STATE_SEND =>\r
	62	if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
	63	SER_OUT <= '1';\r
	64	S_FIFO_READn <= '0';\r
	65	STATE <= STATE_SEND_BIT_0;\r
	66	end if;\r
	67	\r
	68	when STATE_SEND_BIT_0 =>\r
	69	DATUM <= PAR_IN;\r
	70	S_FIFO_READn <= '1';\r
	71	SER_OUT <= PAR_IN(0); \r
	72	STATE <= STATE_SEND_BIT_1;\r
	73	\r
	74	when STATE_SEND_BIT_1 =>\r
	75	SER_OUT <= DATUM(1); \r
	76	STATE <= STATE_SEND_BIT_2;\r
	77	\r
	78	when STATE_SEND_BIT_2 =>\r
	79	SER_OUT <= DATUM(2); \r
	80	STATE <= STATE_SEND_BIT_3;\r
	81	\r
	82	when STATE_SEND_BIT_3 =>\r
	83	SER_OUT <= DATUM(3); \r
	84	STATE <= STATE_SEND_BIT_4;\r
	85	\r
	86	when STATE_SEND_BIT_4 =>\r
	87	SER_OUT <= DATUM(4); \r
	88	STATE <= STATE_SEND_BIT_5;\r
	89	\r
	90	when STATE_SEND_BIT_5 =>\r
	91	SER_OUT <= DATUM(5); \r
	92	STATE <= STATE_SEND_BIT_6;\r
	93	\r
	94	when STATE_SEND_BIT_6 =>\r
	95	SER_OUT <= DATUM(6); \r
	96	STATE <= STATE_SEND_BIT_7;\r
	97	\r
	98	when STATE_SEND_BIT_7 =>\r
	99	SER_OUT <= DATUM(7); \r
	100	STATE <= STATE_END;\r
	101	\r
	102	when STATE_END =>\r
	103	SER_OUT <= '0';\r
	104	STATE <= STATE_SEND;\r
	105	\r
	106	when others => STATE <= STATE_END;\r
	107	end case;\r
097d51b9	108	else\r
097d51b9	109	S_FIFO_READn <= '1';\r
377c0242	110	end if; -- COUNT\r
	111	end if; -- RESET ... / PSC_ENABLE ...\r
	112	end if; -- PCI_CLOCK ...\r
	113	end process;\r
	114	\r
	115	process(PCI_CLOCK)\r
	116	begin\r
	117	if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
	118	SYNC <= SPC_RDY_IN;\r
	119	end if;\r
	120	end process;\r
	121	\r
	122	\r
	123	end architecture PAR_SER_CON_DESIGN;\r