[raggedstone] / dhwk / source / config_00h.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: CONFIG_00H.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity CONFIG_00H is\r
	port\r
	(\r
	VENDOR_ID			:in		std_logic_vector (15 downto 0);\r
	CONF_DATA_00H	:out	std_logic_vector (31 downto 0)\r
	);\r
end entity CONFIG_00H;\r
\r
architecture CONFIG_00H_DESIGN of CONFIG_00H is\r
\r
-- PCI Configuration Space Header Addr : HEX 00 --\r
\r
 	constant	CONF_DEVICE_ID		:std_logic_vector(31 downto 16) := X"AFFE";--???? \r
--constant	CONF_VENDOR_ID		:std_logic_vector(15 downto  0) := X"BAFF";--???? \r
\r
begin\r
\r
	CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;\r
\r
end architecture CONFIG_00H_DESIGN;\r
Commit	Line	Data
377c0242	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: CONFIG_00H.VHD\r
	5	\r
	6	library IEEE;\r
	7	use IEEE.std_logic_1164.all;\r
	8	\r
	9	entity CONFIG_00H is\r
	10	port\r
	11	(\r
	12	VENDOR_ID :in std_logic_vector (15 downto 0);\r
	13	CONF_DATA_00H :out std_logic_vector (31 downto 0)\r
	14	);\r
	15	end entity CONFIG_00H;\r
	16	\r
	17	architecture CONFIG_00H_DESIGN of CONFIG_00H is\r
	18	\r
	19	-- PCI Configuration Space Header Addr : HEX 00 --\r
	20	\r
	21	constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--???? \r
	22	--constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--???? \r
	23	\r
	24	begin\r
	25	\r
	26	CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;\r
	27	\r
	28	end architecture CONFIG_00H_DESIGN;\r