40a1f26c |
1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// |
3 | //// File name "cur_out_reg.v" //// |
4 | //// //// |
5 | //// This file is part of the "PCI bridge" project //// |
6 | //// http://www.opencores.org/cores/pci/ //// |
7 | //// //// |
8 | //// Author(s): //// |
9 | //// - Miha Dolenc (mihad@opencores.org) //// |
10 | //// //// |
11 | //// All additional information is avaliable in the README //// |
12 | //// file. //// |
13 | //// //// |
14 | //// //// |
15 | ////////////////////////////////////////////////////////////////////// |
16 | //// //// |
17 | //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// |
18 | //// //// |
19 | //// This source file may be used and distributed without //// |
20 | //// restriction provided that this copyright statement is not //// |
21 | //// removed from the file and that any derivative work contains //// |
22 | //// the original copyright notice and the associated disclaimer. //// |
23 | //// //// |
24 | //// This source file is free software; you can redistribute it //// |
25 | //// and/or modify it under the terms of the GNU Lesser General //// |
26 | //// Public License as published by the Free Software Foundation; //// |
27 | //// either version 2.1 of the License, or (at your option) any //// |
28 | //// later version. //// |
29 | //// //// |
30 | //// This source is distributed in the hope that it will be //// |
31 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
32 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
33 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
34 | //// details. //// |
35 | //// //// |
36 | //// You should have received a copy of the GNU Lesser General //// |
37 | //// Public License along with this source; if not, download it //// |
38 | //// from http://www.opencores.org/lgpl.shtml //// |
39 | //// //// |
40 | ////////////////////////////////////////////////////////////////////// |
41 | // |
42 | // CVS Revision History |
43 | // |
44 | // $Log: pci_cur_out_reg.v,v $ |
45 | // Revision 1.1 2007-03-20 17:50:56 sithglan |
46 | // add shit |
47 | // |
48 | // Revision 1.1 2003/01/27 16:49:31 mihad |
49 | // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
50 | // |
51 | // Revision 1.3 2002/02/01 15:25:12 mihad |
52 | // Repaired a few bugs, updated specification, added test bench files and design document |
53 | // |
54 | // Revision 1.2 2001/10/05 08:14:28 mihad |
55 | // Updated all files with inclusion of timescale file for simulation purposes. |
56 | // |
57 | // Revision 1.1.1.1 2001/10/02 15:33:46 mihad |
58 | // New project directory structure |
59 | // |
60 | // |
61 | |
62 | // synopsys translate_off |
63 | `include "timescale.v" |
64 | // synopsys translate_on |
65 | `include "pci_constants.v" |
66 | |
67 | // module is only a backup copy of relevant output registers |
68 | // used in some arhitectures that support IOB registers, which have to have a |
69 | // fanout of 1 |
70 | // Otherwise nothing special in this module |
71 | module pci_cur_out_reg |
72 | ( |
73 | reset_in, |
74 | clk_in, |
75 | frame_in, |
76 | frame_load_in, |
77 | irdy_in, |
78 | devsel_in, |
79 | trdy_in, |
80 | trdy_en_in, |
81 | stop_in, |
82 | ad_load_in, |
83 | cbe_in, |
84 | cbe_en_in, |
85 | mas_ad_in, |
86 | tar_ad_in, |
87 | frame_en_in, |
88 | irdy_en_in, |
89 | |
90 | mas_ad_en_in, |
91 | tar_ad_en_in, |
92 | ad_en_unregistered_in, |
93 | |
94 | par_in, |
95 | par_en_in, |
96 | perr_in, |
97 | perr_en_in, |
98 | serr_in, |
99 | serr_en_in, |
100 | |
101 | frame_out, |
102 | irdy_out, |
103 | devsel_out, |
104 | trdy_out, |
105 | stop_out, |
106 | cbe_out, |
107 | cbe_en_out, |
108 | ad_out, |
109 | frame_en_out, |
110 | irdy_en_out, |
111 | ad_en_out, |
112 | mas_ad_en_out, |
113 | tar_ad_en_out, |
114 | trdy_en_out, |
115 | |
116 | par_out, |
117 | par_en_out, |
118 | perr_out, |
119 | perr_en_out, |
120 | serr_out, |
121 | serr_en_out |
122 | ) ; |
123 | |
124 | input reset_in, clk_in ; |
125 | |
126 | input frame_in ; |
127 | input frame_load_in ; |
128 | input irdy_in ; |
129 | input devsel_in ; |
130 | input trdy_in ; |
131 | input stop_in ; |
132 | input ad_load_in ; |
133 | |
134 | input [3:0] cbe_in ; |
135 | input cbe_en_in ; |
136 | input [31:0] mas_ad_in ; |
137 | input [31:0] tar_ad_in ; |
138 | |
139 | input mas_ad_en_in ; |
140 | input tar_ad_en_in ; |
141 | input ad_en_unregistered_in ; |
142 | |
143 | input frame_en_in, |
144 | irdy_en_in ; |
145 | |
146 | input trdy_en_in ; |
147 | |
148 | input par_in ; |
149 | input par_en_in ; |
150 | input perr_in ; |
151 | input perr_en_in ; |
152 | input serr_in ; |
153 | input serr_en_in ; |
154 | |
155 | output frame_out ; |
156 | reg frame_out ; |
157 | output irdy_out ; |
158 | reg irdy_out ; |
159 | output devsel_out ; |
160 | reg devsel_out ; |
161 | output trdy_out ; |
162 | reg trdy_out ; |
163 | output stop_out ; |
164 | reg stop_out ; |
165 | output [3:0] cbe_out ; |
166 | reg [3:0] cbe_out ; |
167 | output [31:0] ad_out ; |
168 | reg [31:0] ad_out ; |
169 | |
170 | output frame_en_out, |
171 | irdy_en_out, |
172 | ad_en_out, |
173 | cbe_en_out, |
174 | mas_ad_en_out, |
175 | tar_ad_en_out, |
176 | trdy_en_out ; |
177 | |
178 | reg frame_en_out, |
179 | irdy_en_out, |
180 | cbe_en_out, |
181 | mas_ad_en_out, |
182 | tar_ad_en_out, |
183 | trdy_en_out; |
184 | |
185 | output par_out ; |
186 | output par_en_out ; |
187 | output perr_out ; |
188 | output perr_en_out ; |
189 | output serr_out ; |
190 | output serr_en_out ; |
191 | |
192 | reg par_out ; |
193 | reg par_en_out ; |
194 | reg perr_out ; |
195 | reg perr_en_out ; |
196 | reg serr_out ; |
197 | reg serr_en_out ; |
198 | |
199 | assign ad_en_out = mas_ad_en_out || tar_ad_en_out ; |
200 | |
201 | always@(posedge reset_in or posedge clk_in) |
202 | begin |
203 | if ( reset_in ) |
204 | begin |
205 | irdy_out <= #`FF_DELAY 1'b1 ; |
206 | devsel_out <= #`FF_DELAY 1'b1 ; |
207 | trdy_out <= #`FF_DELAY 1'b1 ; |
208 | stop_out <= #`FF_DELAY 1'b1 ; |
209 | frame_en_out <= #`FF_DELAY 1'b0 ; |
210 | irdy_en_out <= #`FF_DELAY 1'b0 ; |
211 | mas_ad_en_out<= #`FF_DELAY 1'b0 ; |
212 | tar_ad_en_out<= #`FF_DELAY 1'b0 ; |
213 | trdy_en_out <= #`FF_DELAY 1'b0 ; |
214 | par_out <= #`FF_DELAY 1'b0 ; |
215 | par_en_out <= #`FF_DELAY 1'b0 ; |
216 | perr_out <= #`FF_DELAY 1'b1 ; |
217 | perr_en_out <= #`FF_DELAY 1'b0 ; |
218 | serr_out <= #`FF_DELAY 1'b1 ; |
219 | serr_en_out <= #`FF_DELAY 1'b0 ; |
220 | cbe_en_out <= #`FF_DELAY 1'b0 ; |
221 | |
222 | end |
223 | else |
224 | begin |
225 | irdy_out <= #`FF_DELAY irdy_in ; |
226 | devsel_out <= #`FF_DELAY devsel_in ; |
227 | trdy_out <= #`FF_DELAY trdy_in ; |
228 | stop_out <= #`FF_DELAY stop_in ; |
229 | frame_en_out <= #`FF_DELAY frame_en_in ; |
230 | irdy_en_out <= #`FF_DELAY irdy_en_in ; |
231 | mas_ad_en_out<= #`FF_DELAY mas_ad_en_in && ad_en_unregistered_in ; |
232 | tar_ad_en_out<= #`FF_DELAY tar_ad_en_in && ad_en_unregistered_in ; |
233 | trdy_en_out <= #`FF_DELAY trdy_en_in ; |
234 | |
235 | par_out <= #`FF_DELAY par_in ; |
236 | par_en_out <= #`FF_DELAY par_en_in ; |
237 | perr_out <= #`FF_DELAY perr_in ; |
238 | perr_en_out <= #`FF_DELAY perr_en_in ; |
239 | serr_out <= #`FF_DELAY serr_in ; |
240 | serr_en_out <= #`FF_DELAY serr_en_in ; |
241 | cbe_en_out <= #`FF_DELAY cbe_en_in ; |
242 | end |
243 | end |
244 | |
245 | always@(posedge reset_in or posedge clk_in) |
246 | begin |
247 | if ( reset_in ) |
248 | cbe_out <= #`FF_DELAY 4'hF ; |
249 | else if ( ad_load_in ) |
250 | cbe_out <= #`FF_DELAY cbe_in ; |
251 | |
252 | end |
253 | |
254 | wire [31:0] ad_source = tar_ad_en_out ? tar_ad_in : mas_ad_in ; |
255 | |
256 | always@(posedge reset_in or posedge clk_in) |
257 | begin |
258 | if ( reset_in ) |
259 | ad_out <= #`FF_DELAY 32'h0000_0000 ; |
260 | else if ( ad_load_in ) |
261 | ad_out <= #`FF_DELAY ad_source ; |
262 | |
263 | end |
264 | |
265 | always@(posedge reset_in or posedge clk_in) |
266 | begin |
267 | if ( reset_in ) |
268 | frame_out <= #`FF_DELAY 1'b1 ; |
269 | else if ( frame_load_in ) |
270 | frame_out <= #`FF_DELAY frame_in ; |
271 | |
272 | end |
273 | |
274 | endmodule |