| 40a1f26c |
1 | ////////////////////////////////////////////////////////////////////// |
| 2 | //// //// |
| 3 | //// File name "out_reg.v" //// |
| 4 | //// //// |
| 5 | //// This file is part of the "PCI bridge" project //// |
| 6 | //// http://www.opencores.org/cores/pci/ //// |
| 7 | //// //// |
| 8 | //// Author(s): //// |
| 9 | //// - Miha Dolenc (mihad@opencores.org) //// |
| 10 | //// //// |
| 11 | //// All additional information is avaliable in the README //// |
| 12 | //// file. //// |
| 13 | //// //// |
| 14 | //// //// |
| 15 | ////////////////////////////////////////////////////////////////////// |
| 16 | //// //// |
| 17 | //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// |
| 18 | //// //// |
| 19 | //// This source file may be used and distributed without //// |
| 20 | //// restriction provided that this copyright statement is not //// |
| 21 | //// removed from the file and that any derivative work contains //// |
| 22 | //// the original copyright notice and the associated disclaimer. //// |
| 23 | //// //// |
| 24 | //// This source file is free software; you can redistribute it //// |
| 25 | //// and/or modify it under the terms of the GNU Lesser General //// |
| 26 | //// Public License as published by the Free Software Foundation; //// |
| 27 | //// either version 2.1 of the License, or (at your option) any //// |
| 28 | //// later version. //// |
| 29 | //// //// |
| 30 | //// This source is distributed in the hope that it will be //// |
| 31 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| 32 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| 33 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
| 34 | //// details. //// |
| 35 | //// //// |
| 36 | //// You should have received a copy of the GNU Lesser General //// |
| 37 | //// Public License along with this source; if not, download it //// |
| 38 | //// from http://www.opencores.org/lgpl.shtml //// |
| 39 | //// //// |
| 40 | ////////////////////////////////////////////////////////////////////// |
| 41 | // |
| 42 | // CVS Revision History |
| 43 | // |
| 44 | // $Log: pci_out_reg.v,v $ |
| 45 | // Revision 1.1 2007-03-20 17:50:56 sithglan |
| 46 | // add shit |
| 47 | // |
| 48 | // Revision 1.1 2003/01/27 16:49:31 mihad |
| 49 | // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
| 50 | // |
| 51 | // Revision 1.3 2002/02/01 15:25:12 mihad |
| 52 | // Repaired a few bugs, updated specification, added test bench files and design document |
| 53 | // |
| 54 | // Revision 1.2 2001/10/05 08:14:28 mihad |
| 55 | // Updated all files with inclusion of timescale file for simulation purposes. |
| 56 | // |
| 57 | // Revision 1.1.1.1 2001/10/02 15:33:46 mihad |
| 58 | // New project directory structure |
| 59 | // |
| 60 | // |
| 61 | |
| 62 | `include "pci_constants.v" |
| 63 | |
| 64 | // synopsys translate_off |
| 65 | `include "timescale.v" |
| 66 | // synopsys translate_on |
| 67 | |
| 68 | // module inferes a single IOB output block as known in FPGA architectures |
| 69 | // It provides data flip flop with clock enable and output enable flip flop with clock enable |
| 70 | // This is tested in Xilinx FPGA - active low output enable |
| 71 | // Check polarity of output enable flip flop for specific architecure. |
| 72 | module pci_out_reg |
| 73 | ( |
| 74 | reset_in, |
| 75 | clk_in, |
| 76 | dat_en_in, |
| 77 | en_en_in, |
| 78 | dat_in, |
| 79 | en_in, |
| 80 | en_out, |
| 81 | dat_out |
| 82 | ); |
| 83 | |
| 84 | input reset_in, |
| 85 | clk_in, |
| 86 | dat_en_in, |
| 87 | en_en_in, |
| 88 | dat_in, |
| 89 | en_in ; |
| 90 | |
| 91 | output dat_out ; |
| 92 | output en_out ; |
| 93 | |
| 94 | reg dat_out, |
| 95 | en_out ; |
| 96 | |
| 97 | `ifdef ACTIVE_LOW_OE |
| 98 | wire en = ~en_in ; |
| 99 | `else |
| 100 | `ifdef ACTIVE_HIGH_OE |
| 101 | wire en = en_in ; |
| 102 | `endif |
| 103 | `endif |
| 104 | |
| 105 | always@(posedge reset_in or posedge clk_in) |
| 106 | begin |
| 107 | if ( reset_in ) |
| 108 | dat_out <= #`FF_DELAY 1'b0 ; |
| 109 | else if ( dat_en_in ) |
| 110 | dat_out <= #`FF_DELAY dat_in ; |
| 111 | end |
| 112 | |
| 113 | always@(posedge reset_in or posedge clk_in) |
| 114 | begin |
| 115 | if ( reset_in ) |
| 116 | `ifdef ACTIVE_LOW_OE |
| 117 | en_out <= #`FF_DELAY 1'b1 ; |
| 118 | `else |
| 119 | `ifdef ACTIVE_HIGH_OE |
| 120 | en_out <= #`FF_DELAY 1'b0 ; |
| 121 | `endif |
| 122 | `endif |
| 123 | else if ( en_en_in ) |
| 124 | en_out <= #`FF_DELAY en ; |
| 125 | end |
| 126 | |
| 127 | endmodule |
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