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1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// |
3 | //// File name "wbr_fifo_control.v" //// |
4 | //// //// |
5 | //// This file is part of the "PCI bridge" project //// |
6 | //// http://www.opencores.org/cores/pci/ //// |
7 | //// //// |
8 | //// Author(s): //// |
9 | //// - Miha Dolenc (mihad@opencores.org) //// |
10 | //// //// |
11 | //// All additional information is avaliable in the README //// |
12 | //// file. //// |
13 | //// //// |
14 | //// //// |
15 | ////////////////////////////////////////////////////////////////////// |
16 | //// //// |
17 | //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// |
18 | //// //// |
19 | //// This source file may be used and distributed without //// |
20 | //// restriction provided that this copyright statement is not //// |
21 | //// removed from the file and that any derivative work contains //// |
22 | //// the original copyright notice and the associated disclaimer. //// |
23 | //// //// |
24 | //// This source file is free software; you can redistribute it //// |
25 | //// and/or modify it under the terms of the GNU Lesser General //// |
26 | //// Public License as published by the Free Software Foundation; //// |
27 | //// either version 2.1 of the License, or (at your option) any //// |
28 | //// later version. //// |
29 | //// //// |
30 | //// This source is distributed in the hope that it will be //// |
31 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
32 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
33 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
34 | //// details. //// |
35 | //// //// |
36 | //// You should have received a copy of the GNU Lesser General //// |
37 | //// Public License along with this source; if not, download it //// |
38 | //// from http://www.opencores.org/lgpl.shtml //// |
39 | //// //// |
40 | ////////////////////////////////////////////////////////////////////// |
41 | // |
42 | // CVS Revision History |
43 | // |
44 | // $Log: pci_wbr_fifo_control.v,v $ |
45 | // Revision 1.1 2007-03-20 17:50:56 sithglan |
46 | // add shit |
47 | // |
48 | // Revision 1.4 2003/08/14 13:06:03 simons |
49 | // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. |
50 | // |
51 | // Revision 1.3 2003/07/29 08:20:11 mihad |
52 | // Found and simulated the problem in the synchronization logic. |
53 | // Repaired the synchronization logic in the FIFOs. |
54 | // |
55 | // Revision 1.2 2003/03/26 13:16:18 mihad |
56 | // Added the reset value parameter to the synchronizer flop module. |
57 | // Added resets to all synchronizer flop instances. |
58 | // Repaired initial sync value in fifos. |
59 | // |
60 | // Revision 1.1 2003/01/27 16:49:31 mihad |
61 | // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
62 | // |
63 | // Revision 1.6 2002/11/27 20:36:12 mihad |
64 | // Changed the code a bit to make it more readable. |
65 | // Functionality not changed in any way. |
66 | // More robust synchronization in fifos is still pending. |
67 | // |
68 | // Revision 1.5 2002/09/30 16:03:04 mihad |
69 | // Added meta flop module for easier meta stable FF identification during synthesis |
70 | // |
71 | // Revision 1.4 2002/09/25 15:53:52 mihad |
72 | // Removed all logic from asynchronous reset network |
73 | // |
74 | // Revision 1.3 2002/02/01 15:25:13 mihad |
75 | // Repaired a few bugs, updated specification, added test bench files and design document |
76 | // |
77 | // Revision 1.2 2001/10/05 08:14:30 mihad |
78 | // Updated all files with inclusion of timescale file for simulation purposes. |
79 | // |
80 | // Revision 1.1.1.1 2001/10/02 15:33:47 mihad |
81 | // New project directory structure |
82 | // |
83 | // |
84 | |
85 | /* FIFO_CONTROL module provides read/write address and status generation for |
86 | FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */ |
87 | `include "pci_constants.v" |
88 | // synopsys translate_off |
89 | `include "timescale.v" |
90 | // synopsys translate_on |
91 | |
92 | module pci_wbr_fifo_control |
93 | ( |
94 | rclock_in, |
95 | wclock_in, |
96 | renable_in, |
97 | wenable_in, |
98 | reset_in, |
99 | flush_in, |
100 | empty_out, |
101 | waddr_out, |
102 | raddr_out, |
103 | rallow_out, |
104 | wallow_out |
105 | ) ; |
106 | |
107 | parameter ADDR_LENGTH = 7 ; |
108 | |
109 | // independent clock inputs - rclock_in = read clock, wclock_in = write clock |
110 | input rclock_in, wclock_in; |
111 | |
112 | // enable inputs - read address changes on rising edge of rclock_in when reads are allowed |
113 | // write address changes on rising edge of wclock_in when writes are allowed |
114 | input renable_in, wenable_in; |
115 | |
116 | // reset input |
117 | input reset_in; |
118 | |
119 | // flush input |
120 | input flush_in ; |
121 | |
122 | // empty status output |
123 | output empty_out; |
124 | |
125 | // read and write addresses outputs |
126 | output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out; |
127 | |
128 | // read and write allow outputs |
129 | output rallow_out, wallow_out ; |
130 | |
131 | // read address register |
132 | reg [(ADDR_LENGTH - 1):0] raddr ; |
133 | |
134 | // write address register |
135 | reg [(ADDR_LENGTH - 1):0] waddr; |
136 | assign waddr_out = waddr ; |
137 | |
138 | // grey code register |
139 | reg [(ADDR_LENGTH - 1):0] wgrey_addr ; |
140 | |
141 | // next write gray address calculation - bitwise xor between address and shifted address |
142 | wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ; |
143 | |
144 | // grey code register |
145 | reg [(ADDR_LENGTH - 1):0] rgrey_addr ; |
146 | |
147 | // next read gray address calculation - bitwise xor between address and shifted address |
148 | wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ; |
149 | |
150 | // FF for registered empty flag |
151 | wire empty ; |
152 | |
153 | // write allow wire |
154 | wire wallow = wenable_in ; |
155 | |
156 | // write allow output assignment |
157 | assign wallow_out = wallow ; |
158 | |
159 | // read allow wire |
160 | wire rallow ; |
161 | |
162 | // clear generation for FFs and registers |
163 | wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation |
164 | |
165 | assign empty_out = empty ; |
166 | |
167 | //rallow generation |
168 | assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty |
169 | |
170 | // rallow output assignment |
171 | assign rallow_out = renable_in ; |
172 | |
173 | // at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary |
174 | // when FIFO is empty, this register provides actual read address, so first location can be read |
175 | reg [(ADDR_LENGTH - 1):0] raddr_plus_one ; |
176 | |
177 | // address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out |
178 | // done for zero wait state burst |
179 | assign raddr_out = rallow ? raddr_plus_one : raddr ; |
180 | |
181 | always@(posedge rclock_in or posedge clear) |
182 | begin |
183 | if (clear) |
184 | begin |
185 | raddr_plus_one <= #`FF_DELAY 2 ; |
186 | raddr <= #`FF_DELAY 1 ; |
187 | end |
188 | else if (flush_in) |
189 | begin |
190 | raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ; |
191 | raddr <= #`FF_DELAY waddr ; |
192 | end |
193 | else if (rallow) |
194 | begin |
195 | raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ; |
196 | raddr <= #`FF_DELAY raddr_plus_one ; |
197 | end |
198 | end |
199 | |
200 | /*----------------------------------------------------------------------------------------------- |
201 | Read address control consists of Read address counter and Grey Address register |
202 | --------------------------------------------------------------------------------------------------*/ |
203 | // grey coded address |
204 | always@(posedge rclock_in or posedge clear) |
205 | begin |
206 | if (clear) |
207 | begin |
208 | rgrey_addr <= #`FF_DELAY 0 ; |
209 | end |
210 | else if (flush_in) |
211 | begin |
212 | rgrey_addr <= #`FF_DELAY wgrey_addr ; // when flushed, copy value from write side |
213 | end |
214 | else if (rallow) |
215 | begin |
216 | rgrey_addr <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ; |
217 | end |
218 | end |
219 | |
220 | /*-------------------------------------------------------------------------------------------- |
221 | Write address control consists of write address counter and Grey Code Register |
222 | ----------------------------------------------------------------------------------------------*/ |
223 | // grey coded address for status generation in write clock domain |
224 | always@(posedge wclock_in or posedge clear) |
225 | begin |
226 | if (clear) |
227 | begin |
228 | wgrey_addr <= #1 0 ; |
229 | end |
230 | else |
231 | if (wallow) |
232 | begin |
233 | wgrey_addr <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
234 | end |
235 | end |
236 | |
237 | // write address counter - nothing special except initial value |
238 | always@(posedge wclock_in or posedge clear) |
239 | begin |
240 | if (clear) |
241 | // initial value is 1 |
242 | waddr <= #`FF_DELAY 1 ; |
243 | else |
244 | if (wallow) |
245 | waddr <= #`FF_DELAY waddr + 1'b1 ; |
246 | end |
247 | |
248 | |
249 | /*------------------------------------------------------------------------------------------------------------------------------ |
250 | Empty control: |
251 | Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer. |
252 | If they are equal, fifo is empty. |
253 | --------------------------------------------------------------------------------------------------------------------------------*/ |
254 | wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ; |
255 | reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ; |
256 | pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr |
257 | ( |
258 | .data_in (wgrey_addr), |
259 | .clk_out (rclock_in), |
260 | .sync_data_out (rclk_sync_wgrey_addr), |
261 | .async_reset (clear) |
262 | ) ; |
263 | |
264 | always@(posedge rclock_in or posedge clear) |
265 | begin |
266 | if (clear) |
267 | rclk_wgrey_addr <= #`FF_DELAY 0 ; |
268 | else |
269 | rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ; |
270 | end |
271 | |
272 | assign empty = (rgrey_addr == rclk_wgrey_addr) ; |
273 | endmodule |