]> cvs.zerfleddert.de Git - raggedstone/blame - dhwk/source/pci/parity_4.vhd
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
[raggedstone] / dhwk / source / pci / parity_4.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: PARITY_4.VHD
5
6library ieee;
7use ieee.std_logic_1164.all;
8
9entity PARITY_4 is
2612d712 10 port
11 (
12 PAR_IN :in std_logic_vector(3 downto 0);
13 PAR_OUT :out std_logic
14 );
15end entity PARITY_4;
696ded12 16
17architecture PARITY_4_DESIGN of PARITY_4 is
18
19begin
20
2612d712 21 PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
696ded12 22
23end architecture PARITY_4_DESIGN;
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