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[raggedstone] / dhwk / source / pci / address_register.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: ADDR_REG.VHD

library IEEE;
use IEEE.std_logic_1164.all;

entity ADDRESS_REGISTER is
	port (
                PCI_CLOCK	:in	std_logic;
                PCI_RSTn	:in	std_logic;
                LOAD_ADDR_REG	:in	std_logic;
                AD_REG		:in	std_logic_vector (31 downto 0);
                ADDR_REG	:out	std_logic_vector (31 downto 0)
        );
end entity ADDRESS_REGISTER;

architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
begin 

	process (PCI_CLOCK, PCI_RSTn) 
	begin
		if	PCI_RSTn = '0'	then
                        REG_ADDR	<= X"00000000";

		elsif (rising_edge(PCI_CLOCK)) then
			if LOAD_ADDR_REG = '1' then
                                REG_ADDR	<=	AD_REG;
			else
                                REG_ADDR	<=	REG_ADDR;
			end if;
		end if;
	end process;

	ADDR_REG	<=	REG_ADDR;

end architecture ADDR_REGI_DESIGN;