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[raggedstone] / dhwk / source / pci / io_mux_reg.vhd

-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity IO_MUX_REG is
        Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
               LOAD_ADDR_REG : In std_logic;
               PCI_CBEn : In std_logic_vector (3 downto 0);
               PCI_CLOCK : In std_logic;
               PCI_FRAMEn : In std_logic;
               PCI_IDSEL : In std_logic;
               PCI_IRDYn : In std_logic;
               PCI_PAR : In std_logic;
               PCI_RSTn : In std_logic;
               READ_SEL : In std_logic_vector (1 downto 0);
               USER_DATA : In std_logic_vector (31 downto 0);
               PCI_AD : InOut std_logic_vector (31 downto 0);
               AD_REG : Out std_logic_vector (31 downto 0);
               ADDR_REG : Out std_logic_vector (31 downto 0);
               CBE_REGn : Out std_logic_vector (3 downto 0);
               FRAME_REGn : Out std_logic;
               IDSEL_REG : Out std_logic;
               IRDY_REGn : Out std_logic;
               PAR_REG : Out std_logic );
end IO_MUX_REG;

architecture SCHEMATIC of IO_MUX_REG is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal IO_DATA : std_logic_vector (31 downto 0);
        signal AD_REG_DUMMY : std_logic_vector (31 downto 0);

        component ADDRESS_REGISTER
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       LOAD_ADDR_REG : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       ADDR_REG : Out std_logic_vector (31 downto 0) );
        end component;

        component IO_REG
                Port ( IO_DATA : In std_logic_vector (31 downto 0);
                       OE_PCI_AD : In std_logic;
                       PCI_CBEn : In std_logic_vector (3 downto 0);
                       PCI_CLOCK : In std_logic;
                       PCI_FRAMEn : In std_logic;
                       PCI_IDSEL : In std_logic;
                       PCI_IRDYn : In std_logic;
                       PCI_PAR : In std_logic;
                       PCI_RSTn : In std_logic;
                       AD_REG : Out std_logic_vector (31 downto 0);
                       CBE_REGn : Out std_logic_vector (3 downto 0);
                       FRAME_REGn : Out std_logic;
                       IDSEL_REG : Out std_logic;
                       IRDY_REGn : Out std_logic;
                       PAR_REG : Out std_logic;
                       PCI_AD : Out std_logic_vector (31 downto 0) );
        end component;

        component IO_MUX
                Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
                       PCI_AD : In std_logic_vector (31 downto 0);
                       READ_SEL : In std_logic_vector (1 downto 0);
                       USER_DATA : In std_logic_vector (31 downto 0);
                       IO_DATA : Out std_logic_vector (31 downto 0) );
        end component;

begin

        AD_REG <= AD_REG_DUMMY;

        I5 : ADDRESS_REGISTER
        Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                   LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
                   PCI_RSTn=>PCI_RSTn,
                   ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );
        I1 : IO_REG
        Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),
                   OE_PCI_AD=>READ_SEL(1),
                   PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
                   PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
                   PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
                   PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
                   AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                   CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
                   FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
                   IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,
                   PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );
        I2 : IO_MUX
        Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),
        PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
        READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
        USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),
        IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );

end SCHEMATIC;