[raggedstone] / dhwk / source / pci / top.vhd

-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity dhwk is
        Port ( KONST_1 : In std_logic;
               PCI_CBEn : In std_logic_vector (3 downto 0);
               PCI_CLOCK : In std_logic;
               PCI_FRAMEn : In std_logic;
               PCI_IDSEL : In std_logic;
               PCI_IRDYn : In std_logic;
               PCI_RSTn : In std_logic;
               -- SERIAL_IN : In std_logic;
               -- SPC_RDY_IN : In std_logic;
               TAST_RESn : In std_logic;
               TAST_SETn : In std_logic;
               LED_2 : out std_logic;
               LED_3 : out std_logic;
               LED_4 : out std_logic;
               LED_5 : out std_logic;
               PCI_AD : InOut std_logic_vector (31 downto 0);
               PCI_PAR : InOut std_logic;
               PCI_DEVSELn : Out std_logic;
               PCI_INTAn : Out std_logic;
               PCI_PERRn : Out std_logic;
               PCI_SERRn : Out std_logic;
               PCI_STOPn : Out std_logic;
               PCI_TRDYn : Out std_logic;
               PCI_REQn : Out std_logic;
               PCI_GNTn : In std_logic;
               -- SERIAL_OUT : Out std_logic;
               -- SPC_RDY_OUT : Out std_logic;
               TB_IDSEL : Out std_logic;
               TB_nDEVSEL : Out std_logic;
               TB_nINTA : Out std_logic );
end dhwk;

architecture SCHEMATIC of dhwk is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal READ_XX7_6 : std_logic;
        signal RESERVE : std_logic;
        signal SR_ERROR : std_logic;
        signal R_ERROR : std_logic;
        signal S_ERROR : std_logic;
        signal WRITE_XX3_2 : std_logic;
        signal WRITE_XX5_4 : std_logic;
        signal WRITE_XX7_6 : std_logic;
        signal READ_XX1_0 : std_logic;
        signal READ_XX3_2 : std_logic;
        signal INTAn : std_logic;
        signal TRDYn : std_logic;
        signal READ_XX5_4 : std_logic;
        signal DEVSELn : std_logic;
        signal FIFO_RDn : std_logic;
        signal WRITE_XX1_0 : std_logic;
        signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
        signal SYNC_FLAG : std_logic_vector (7 downto 0);
        signal INT_REG : std_logic_vector (7 downto 0);
        signal REVISON_ID : std_logic_vector (7 downto 0);
        signal VENDOR_ID : std_logic_vector (15 downto 0);
        signal READ_SEL : std_logic_vector (1 downto 0);
        signal AD_REG : std_logic_vector (31 downto 0);
        signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
        signal R_EFn : std_logic;
        signal R_FFn : std_logic;
        signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
        signal R_HFn : std_logic;
        signal S_EFn : std_logic;
        signal S_FFn : std_logic;
        signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
        signal S_HFn : std_logic;
        signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
        signal R_FIFO_READn : std_logic;
        signal R_FIFO_RESETn : std_logic;
        signal R_FIFO_RTn : std_logic;
        signal R_FIFO_WRITEn : std_logic;
        signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
        signal S_FIFO_READn : std_logic;
        signal S_FIFO_RESETn : std_logic;
        signal S_FIFO_RTn : std_logic;
        signal S_FIFO_WRITEn : std_logic;
        signal SERIAL_IN : std_logic;
        signal SPC_RDY_IN : std_logic;
        signal SERIAL_OUT : std_logic;
        signal SPC_RDY_OUT : std_logic;
        signal watch_PCI_INTAn : std_logic;
        signal watch_PCI_TRDYn : std_logic;
        signal watch_PCI_STOPn : std_logic;
        signal watch_PCI_SERRn : std_logic;
        signal watch_PCI_PERRn : std_logic;
        signal watch_PCI_REQn : std_logic;
        signal control0 : std_logic_vector(35 downto 0);
        signal control1 : std_logic_vector(35 downto 0);
        signal data : std_logic_vector(95 downto 0);
        signal trig0 : std_logic_vector(31 downto 0);
	signal vio_async_out : std_logic_vector(0 downto 0);

        component MESS_1_TB
                Port ( DEVSELn : In std_logic;
                       INTAn : In std_logic;
                       KONST_1 : In std_logic;
                       PCI_IDSEL : In std_logic;
                       REG_OUT_XX7 : In std_logic_vector (7 downto 0);
                       TB_DEVSELn : Out std_logic;
                       TB_INTAn : Out std_logic;
                       TB_PCI_IDSEL : Out std_logic );
        end component;

        component VEN_REV_ID
                Port ( REV_ID : Out std_logic_vector (7 downto 0);
                       VEN_ID : Out std_logic_vector (15 downto 0) );
        end component;

        component INTERRUPT
                Port ( INT_IN_0 : In std_logic;
                       INT_IN_1 : In std_logic;
                       INT_IN_2 : In std_logic;
                       INT_IN_3 : In std_logic;
                       INT_IN_4 : In std_logic;
                       INT_IN_5 : In std_logic;
                       INT_IN_6 : In std_logic;
                       INT_IN_7 : In std_logic;
                       INT_MASKE : In std_logic_vector (7 downto 0);
                       INT_RES : In std_logic_vector (7 downto 0);
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       READ_XX5_4 : In std_logic;
                       RESET : In std_logic;
                       TAST_RESn : In std_logic;
                       TAST_SETn : In std_logic;
                       TRDYn : In std_logic;
                       INT_REG : Out std_logic_vector (7 downto 0);
                       INTAn : Out std_logic;
                       PCI_INTAn : Out std_logic );
        end component;

        component FIFO_CONTROL
                Port ( FIFO_RDn : In std_logic;
                       FLAG_IN_0 : In std_logic;
                       FLAG_IN_4 : In std_logic;
                       HOLD : In std_logic;
                       KONST_1 : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PSC_ENABLE : In std_logic;
                       R_EFn : In std_logic;
                       R_FFn : In std_logic;
                       R_HFn : In std_logic;
                       RESET : In std_logic;
                       S_EFn : In std_logic;
                       S_FFn : In std_logic;
                       S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
                       S_HFn : In std_logic;
                       SERIAL_IN : In std_logic;
                       SPC_ENABLE : In std_logic;
                       SPC_RDY_IN : In std_logic;
                       WRITE_XX1_0 : In std_logic;
                       R_ERROR : Out std_logic;
                       R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
                       R_FIFO_READn : Out std_logic;
                       R_FIFO_RESETn : Out std_logic;
                       R_FIFO_RETRANSMITn : Out std_logic;
                       R_FIFO_WRITEn : Out std_logic;
                       RESERVE : Out std_logic;
                       S_ERROR : Out std_logic;
                       S_FIFO_READn : Out std_logic;
                       S_FIFO_RESETn : Out std_logic;
                       S_FIFO_RETRANSMITn : Out std_logic;
                       S_FIFO_WRITEn : Out std_logic;
                       SERIAL_OUT : Out std_logic;
                       SPC_RDY_OUT : Out std_logic;
                       SR_ERROR : Out std_logic;
                       SYNC_FLAG : Out std_logic_vector (7 downto 0) );
        end component;

        component PCI_TOP
                Port ( FLAG : In std_logic_vector (7 downto 0);
                       INT_REG : In std_logic_vector (7 downto 0);
                       PCI_CBEn : In std_logic_vector (3 downto 0);
                       PCI_CLOCK : In std_logic;
                       PCI_FRAMEn : In std_logic;
                       PCI_IDSEL : In std_logic;
                       PCI_IRDYn : In std_logic;
                       PCI_RSTn : In std_logic;
                       R_FIFO_Q : In std_logic_vector (7 downto 0);
                       REVISON_ID : In std_logic_vector (7 downto 0);
                       VENDOR_ID : In std_logic_vector (15 downto 0);
                       PCI_AD : InOut std_logic_vector (31 downto 0);
                       PCI_PAR : InOut std_logic;
                       AD_REG : Out std_logic_vector (31 downto 0);
                       DEVSELn : Out std_logic;
                       FIFO_RDn : Out std_logic;
                       PCI_DEVSELn : Out std_logic;
                       PCI_PERRn : Out std_logic;
                       PCI_SERRn : Out std_logic;
                       PCI_STOPn : Out std_logic;
                       PCI_TRDYn : Out std_logic;
                       READ_SEL : Out std_logic_vector (1 downto 0);
                       READ_XX1_0 : Out std_logic;
                       READ_XX3_2 : Out std_logic;
                       READ_XX5_4 : Out std_logic;
                       READ_XX7_6 : Out std_logic;
                       REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
                       REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
                       REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
                       TRDYn : Out std_logic;
                       WRITE_XX1_0 : Out std_logic;
                       WRITE_XX3_2 : Out std_logic;
                       WRITE_XX5_4 : Out std_logic;
                       WRITE_XX7_6 : Out std_logic );
        end component;

        component dhwk_fifo
                port (
                             clk: IN std_logic;
                             din: IN std_logic_VECTOR(7 downto 0);
                             rd_en: IN std_logic;
                             rst: IN std_logic;
                             wr_en: IN std_logic;
                             almost_empty: OUT std_logic;
                             almost_full: OUT std_logic;
                             dout: OUT std_logic_VECTOR(7 downto 0);
                             empty: OUT std_logic;
                             full: OUT std_logic;
                             prog_full: OUT std_logic);
        end component;

        component icon
                port
                (
                        control0 : out std_logic_vector(35 downto 0);
                        control1 : out std_logic_vector(35 downto 0)
                );
        end component;

        component ila
                port
                (
                        control : in std_logic_vector(35 downto 0);
                        clk : in std_logic;
                        data : in std_logic_vector(95 downto 0);
                        trig0 : in std_logic_vector(31 downto 0)
                );
        end component;

	component vio
		port
		(
			control : in std_logic_vector(35 downto 0);
			async_out : out std_logic_vector(0 downto 0)
		);
	end component;


begin
        watch_PCI_REQn <= '1';
        SERIAL_IN <= SERIAL_OUT;
        SPC_RDY_IN <= SPC_RDY_OUT;
        LED_2 <= not PCI_RSTn;
        LED_3 <= not PCI_IDSEL;
        LED_4 <= not PCI_FRAMEn;
        LED_5 <= not watch_PCI_INTAn;
        PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0));

        trig0(31 downto 0) <= (
        0 => watch_PCI_INTAn,
        1 => R_FIFO_READn,
        2 => R_FIFO_WRITEn,
        3 => S_FIFO_READn,
        4 => S_FIFO_WRITEn,
        5 => PCI_RSTn,
	6 => PCI_IDSEL,
        16 => PCI_AD(0),
        17 => PCI_AD(1),
        18 => PCI_AD(2),
        19 => PCI_AD(3),
        20 => PCI_AD(4),
        21 => PCI_AD(5),
        22 => PCI_AD(6),
        23 => PCI_AD(7),
        27 => PCI_FRAMEn,
        28 => PCI_CBEn(0),
        29 => PCI_CBEn(1),
        30 => PCI_CBEn(2),
        31 => PCI_CBEn(3),
        others => '0');

        data(0) <= watch_PCI_INTAn;
        data(1) <= R_EFn;
        data(2) <= R_HFn;
        data(3) <= R_FFn;
        data(4) <= R_FIFO_READn;
        data(5) <= R_FIFO_RESETn;
        data(6) <= R_FIFO_RTn;
        data(7) <= R_FIFO_WRITEn;
        data(8) <= S_EFn;
        data(9) <= S_HFn;
        data(10) <= S_FFn;
        data(11) <= S_FIFO_READn;
        data(12) <= S_FIFO_RESETn;
        data(13) <= S_FIFO_RTn;
        data(14) <= S_FIFO_WRITEn;
        data(15) <= SERIAL_IN;
        data(16) <= SPC_RDY_IN;
        data(17) <= SERIAL_OUT;
        data(18) <= SPC_RDY_OUT;
        data(26 downto 19) <= S_FIFO_Q_OUT;
        data(34 downto 27) <= R_FIFO_Q_OUT;
        data(66 downto 35) <= PCI_AD(31 downto 0);
        data(70 downto 67) <= PCI_CBEn(3 downto 0);
        data(71) <= PCI_FRAMEn;
        data(72) <= PCI_IDSEL;
        PCI_TRDYn <= watch_PCI_TRDYn;
        data(73) <= watch_PCI_TRDYn;
        data(74) <= PCI_IRDYn;
        PCI_STOPn <= watch_PCI_STOPn;
        data(75) <= watch_PCI_STOPn;
        PCI_SERRn <= watch_PCI_SERRn;
        data(76) <= watch_PCI_SERRn;
        PCI_PERRn <= watch_PCI_PERRn;
        data(77) <= watch_PCI_PERRn;
        PCI_REQn <= watch_PCI_REQn;
        data(78) <= watch_PCI_REQn;
        data(79) <= PCI_GNTn;

        I19 : MESS_1_TB
        Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
                   PCI_IDSEL=>PCI_IDSEL,
                   REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
                   TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
                   TB_PCI_IDSEL=>TB_IDSEL );
        I18 : VEN_REV_ID
        Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
        VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
        I16 : INTERRUPT
        Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
                   INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
                   INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
                   INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
                   INT_RES(7 downto 0)=>AD_REG(7 downto 0),
                   PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
                   READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                   TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                   TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
                   INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
        I14 : FIFO_CONTROL
        Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                   FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
                   PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
                   R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
                   RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
                   S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
                   S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
                   SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
                   WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
                   R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
                   R_FIFO_READn=>R_FIFO_READn,
                   R_FIFO_RESETn=>R_FIFO_RESETn,
                   R_FIFO_RETRANSMITn=>R_FIFO_RTn,
                   R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
                   S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
                   S_FIFO_RESETn=>S_FIFO_RESETn,
                   S_FIFO_RETRANSMITn=>S_FIFO_RTn,
                   S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
                   SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
                   SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
        I1 : PCI_TOP
        Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
        INT_REG(7 downto 0)=>INT_REG(7 downto 0),
        PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
        PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
        PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
        PCI_RSTn=>PCI_RSTn,
        R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
        REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
        VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
        PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
        PCI_PAR=>PCI_PAR,
        AD_REG(31 downto 0)=>AD_REG(31 downto 0),
        DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
        PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
        PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
        PCI_TRDYn=>watch_PCI_TRDYn,
        READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
        READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
        READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
        REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
        REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
        REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
        TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
        WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
        WRITE_XX7_6=>WRITE_XX7_6 );

        receive_fifo : dhwk_fifo
        port map (
                         clk => PCI_CLOCK,
                         din => R_FIFO_D_IN,
                         rd_en => not R_FIFO_READn,
                         rst => not R_FIFO_RESETn,
                         wr_en => not R_FIFO_WRITEn,
                         dout => R_FIFO_Q_OUT,
                         empty => R_EFn,
                         full => R_FFn,
                         prog_full => R_HFn);

        send_fifo : dhwk_fifo
        port map (
                         clk => PCI_CLOCK,
                         din => S_FIFO_D_IN,
                         rd_en => not S_FIFO_READn,
                         rst => not S_FIFO_RESETn,
                         wr_en => not S_FIFO_WRITEn,
                         dout => S_FIFO_Q_OUT,
                         empty => S_EFn,
                         full => S_FFn,
                         prog_full => S_HFn);

        i_icon : icon
        port map
        (
                control0 => control0,
                control1 => control1
        );

        i_ila : ila
        port map
        (
                control => control0,
                clk => PCI_CLOCK,
                data => data,
                trig0 => trig0
        );

	i_vio : vio
	port map
	(
		control => control1,
		async_out => vio_async_out
	);
end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
696ded12	2
696ded12	3	LIBRARY ieee;
	4
	5	USE ieee.std_logic_1164.ALL;
	6	USE ieee.numeric_std.ALL;
	7
	8
	9	entity dhwk is
2612d712	10	Port ( KONST_1 : In std_logic;
	11	PCI_CBEn : In std_logic_vector (3 downto 0);
	12	PCI_CLOCK : In std_logic;
	13	PCI_FRAMEn : In std_logic;
	14	PCI_IDSEL : In std_logic;
	15	PCI_IRDYn : In std_logic;
	16	PCI_RSTn : In std_logic;
	17	-- SERIAL_IN : In std_logic;
	18	-- SPC_RDY_IN : In std_logic;
	19	TAST_RESn : In std_logic;
	20	TAST_SETn : In std_logic;
	21	LED_2 : out std_logic;
	22	LED_3 : out std_logic;
	23	LED_4 : out std_logic;
	24	LED_5 : out std_logic;
	25	PCI_AD : InOut std_logic_vector (31 downto 0);
	26	PCI_PAR : InOut std_logic;
	27	PCI_DEVSELn : Out std_logic;
	28	PCI_INTAn : Out std_logic;
	29	PCI_PERRn : Out std_logic;
	30	PCI_SERRn : Out std_logic;
	31	PCI_STOPn : Out std_logic;
	32	PCI_TRDYn : Out std_logic;
	33	PCI_REQn : Out std_logic;
	34	PCI_GNTn : In std_logic;
	35	-- SERIAL_OUT : Out std_logic;
	36	-- SPC_RDY_OUT : Out std_logic;
	37	TB_IDSEL : Out std_logic;
	38	TB_nDEVSEL : Out std_logic;
	39	TB_nINTA : Out std_logic );
696ded12	40	end dhwk;
	41
	42	architecture SCHEMATIC of dhwk is
	43
2612d712	44	SIGNAL gnd : std_logic := '0';
2612d712	45	SIGNAL vcc : std_logic := '1';
696ded12	46
2612d712	47	signal READ_XX7_6 : std_logic;
	48	signal RESERVE : std_logic;
	49	signal SR_ERROR : std_logic;
	50	signal R_ERROR : std_logic;
	51	signal S_ERROR : std_logic;
	52	signal WRITE_XX3_2 : std_logic;
	53	signal WRITE_XX5_4 : std_logic;
	54	signal WRITE_XX7_6 : std_logic;
	55	signal READ_XX1_0 : std_logic;
	56	signal READ_XX3_2 : std_logic;
	57	signal INTAn : std_logic;
	58	signal TRDYn : std_logic;
	59	signal READ_XX5_4 : std_logic;
	60	signal DEVSELn : std_logic;
	61	signal FIFO_RDn : std_logic;
	62	signal WRITE_XX1_0 : std_logic;
	63	signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
	64	signal SYNC_FLAG : std_logic_vector (7 downto 0);
	65	signal INT_REG : std_logic_vector (7 downto 0);
	66	signal REVISON_ID : std_logic_vector (7 downto 0);
	67	signal VENDOR_ID : std_logic_vector (15 downto 0);
	68	signal READ_SEL : std_logic_vector (1 downto 0);
	69	signal AD_REG : std_logic_vector (31 downto 0);
	70	signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
	71	signal R_EFn : std_logic;
	72	signal R_FFn : std_logic;
	73	signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
	74	signal R_HFn : std_logic;
	75	signal S_EFn : std_logic;
	76	signal S_FFn : std_logic;
	77	signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
	78	signal S_HFn : std_logic;
	79	signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
	80	signal R_FIFO_READn : std_logic;
	81	signal R_FIFO_RESETn : std_logic;
	82	signal R_FIFO_RTn : std_logic;
	83	signal R_FIFO_WRITEn : std_logic;
	84	signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
	85	signal S_FIFO_READn : std_logic;
	86	signal S_FIFO_RESETn : std_logic;
	87	signal S_FIFO_RTn : std_logic;
	88	signal S_FIFO_WRITEn : std_logic;
	89	signal SERIAL_IN : std_logic;
	90	signal SPC_RDY_IN : std_logic;
	91	signal SERIAL_OUT : std_logic;
	92	signal SPC_RDY_OUT : std_logic;
	93	signal watch_PCI_INTAn : std_logic;
	94	signal watch_PCI_TRDYn : std_logic;
	95	signal watch_PCI_STOPn : std_logic;
	96	signal watch_PCI_SERRn : std_logic;
	97	signal watch_PCI_PERRn : std_logic;
	98	signal watch_PCI_REQn : std_logic;
	99	signal control0 : std_logic_vector(35 downto 0);
cf1ee28a	100	signal control1 : std_logic_vector(35 downto 0);
2612d712	101	signal data : std_logic_vector(95 downto 0);
2612d712	102	signal trig0 : std_logic_vector(31 downto 0);
cf1ee28a	103	signal vio_async_out : std_logic_vector(0 downto 0);
696ded12	104
2612d712	105	component MESS_1_TB
	106	Port ( DEVSELn : In std_logic;
	107	INTAn : In std_logic;
	108	KONST_1 : In std_logic;
	109	PCI_IDSEL : In std_logic;
	110	REG_OUT_XX7 : In std_logic_vector (7 downto 0);
	111	TB_DEVSELn : Out std_logic;
	112	TB_INTAn : Out std_logic;
	113	TB_PCI_IDSEL : Out std_logic );
	114	end component;
696ded12	115
2612d712	116	component VEN_REV_ID
	117	Port ( REV_ID : Out std_logic_vector (7 downto 0);
	118	VEN_ID : Out std_logic_vector (15 downto 0) );
	119	end component;
696ded12	120
2612d712	121	component INTERRUPT
	122	Port ( INT_IN_0 : In std_logic;
	123	INT_IN_1 : In std_logic;
	124	INT_IN_2 : In std_logic;
	125	INT_IN_3 : In std_logic;
	126	INT_IN_4 : In std_logic;
	127	INT_IN_5 : In std_logic;
	128	INT_IN_6 : In std_logic;
	129	INT_IN_7 : In std_logic;
	130	INT_MASKE : In std_logic_vector (7 downto 0);
	131	INT_RES : In std_logic_vector (7 downto 0);
	132	PCI_CLOCK : In std_logic;
	133	PCI_RSTn : In std_logic;
	134	READ_XX5_4 : In std_logic;
	135	RESET : In std_logic;
	136	TAST_RESn : In std_logic;
	137	TAST_SETn : In std_logic;
	138	TRDYn : In std_logic;
	139	INT_REG : Out std_logic_vector (7 downto 0);
	140	INTAn : Out std_logic;
	141	PCI_INTAn : Out std_logic );
	142	end component;
696ded12	143
2612d712	144	component FIFO_CONTROL
	145	Port ( FIFO_RDn : In std_logic;
	146	FLAG_IN_0 : In std_logic;
	147	FLAG_IN_4 : In std_logic;
	148	HOLD : In std_logic;
	149	KONST_1 : In std_logic;
	150	PCI_CLOCK : In std_logic;
	151	PSC_ENABLE : In std_logic;
	152	R_EFn : In std_logic;
	153	R_FFn : In std_logic;
	154	R_HFn : In std_logic;
	155	RESET : In std_logic;
	156	S_EFn : In std_logic;
	157	S_FFn : In std_logic;
	158	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
	159	S_HFn : In std_logic;
	160	SERIAL_IN : In std_logic;
	161	SPC_ENABLE : In std_logic;
	162	SPC_RDY_IN : In std_logic;
	163	WRITE_XX1_0 : In std_logic;
	164	R_ERROR : Out std_logic;
	165	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
	166	R_FIFO_READn : Out std_logic;
	167	R_FIFO_RESETn : Out std_logic;
	168	R_FIFO_RETRANSMITn : Out std_logic;
	169	R_FIFO_WRITEn : Out std_logic;
	170	RESERVE : Out std_logic;
	171	S_ERROR : Out std_logic;
	172	S_FIFO_READn : Out std_logic;
	173	S_FIFO_RESETn : Out std_logic;
	174	S_FIFO_RETRANSMITn : Out std_logic;
	175	S_FIFO_WRITEn : Out std_logic;
	176	SERIAL_OUT : Out std_logic;
	177	SPC_RDY_OUT : Out std_logic;
	178	SR_ERROR : Out std_logic;
	179	SYNC_FLAG : Out std_logic_vector (7 downto 0) );
	180	end component;
696ded12	181
2612d712	182	component PCI_TOP
	183	Port ( FLAG : In std_logic_vector (7 downto 0);
	184	INT_REG : In std_logic_vector (7 downto 0);
	185	PCI_CBEn : In std_logic_vector (3 downto 0);
	186	PCI_CLOCK : In std_logic;
	187	PCI_FRAMEn : In std_logic;
	188	PCI_IDSEL : In std_logic;
	189	PCI_IRDYn : In std_logic;
	190	PCI_RSTn : In std_logic;
	191	R_FIFO_Q : In std_logic_vector (7 downto 0);
	192	REVISON_ID : In std_logic_vector (7 downto 0);
	193	VENDOR_ID : In std_logic_vector (15 downto 0);
	194	PCI_AD : InOut std_logic_vector (31 downto 0);
	195	PCI_PAR : InOut std_logic;
	196	AD_REG : Out std_logic_vector (31 downto 0);
	197	DEVSELn : Out std_logic;
	198	FIFO_RDn : Out std_logic;
	199	PCI_DEVSELn : Out std_logic;
	200	PCI_PERRn : Out std_logic;
	201	PCI_SERRn : Out std_logic;
	202	PCI_STOPn : Out std_logic;
	203	PCI_TRDYn : Out std_logic;
	204	READ_SEL : Out std_logic_vector (1 downto 0);
	205	READ_XX1_0 : Out std_logic;
	206	READ_XX3_2 : Out std_logic;
	207	READ_XX5_4 : Out std_logic;
	208	READ_XX7_6 : Out std_logic;
	209	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
	210	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
	211	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
	212	TRDYn : Out std_logic;
	213	WRITE_XX1_0 : Out std_logic;
	214	WRITE_XX3_2 : Out std_logic;
	215	WRITE_XX5_4 : Out std_logic;
	216	WRITE_XX7_6 : Out std_logic );
	217	end component;
696ded12	218
2612d712	219	component dhwk_fifo
	220	port (
	221	clk: IN std_logic;
	222	din: IN std_logic_VECTOR(7 downto 0);
	223	rd_en: IN std_logic;
	224	rst: IN std_logic;
	225	wr_en: IN std_logic;
	226	almost_empty: OUT std_logic;
	227	almost_full: OUT std_logic;
	228	dout: OUT std_logic_VECTOR(7 downto 0);
	229	empty: OUT std_logic;
	230	full: OUT std_logic;
	231	prog_full: OUT std_logic);
	232	end component;
696ded12	233
2612d712	234	component icon
	235	port
	236	(
cf1ee28a	237	control0 : out std_logic_vector(35 downto 0);
cf1ee28a	238	control1 : out std_logic_vector(35 downto 0)
2612d712	239	);
2612d712	240	end component;
696ded12	241
2612d712	242	component ila
	243	port
	244	(
	245	control : in std_logic_vector(35 downto 0);
	246	clk : in std_logic;
	247	data : in std_logic_vector(95 downto 0);
	248	trig0 : in std_logic_vector(31 downto 0)
	249	);
	250	end component;
696ded12	251
cf1ee28a	252	component vio
	253	port
	254	(
	255	control : in std_logic_vector(35 downto 0);
	256	async_out : out std_logic_vector(0 downto 0)
	257	);
	258	end component;
	259
696ded12	260
696ded12	261	begin
2612d712	262	watch_PCI_REQn <= '1';
	263	SERIAL_IN <= SERIAL_OUT;
	264	SPC_RDY_IN <= SPC_RDY_OUT;
	265	LED_2 <= not PCI_RSTn;
79de9a8a	266	LED_3 <= not PCI_IDSEL;
2612d712	267	LED_4 <= not PCI_FRAMEn;
2612d712	268	LED_5 <= not watch_PCI_INTAn;
cf1ee28a	269	PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0));
cf1ee28a	270
2612d712	271	trig0(31 downto 0) <= (
	272	0 => watch_PCI_INTAn,
	273	1 => R_FIFO_READn,
	274	2 => R_FIFO_WRITEn,
	275	3 => S_FIFO_READn,
	276	4 => S_FIFO_WRITEn,
	277	5 => PCI_RSTn,
79de9a8a	278	6 => PCI_IDSEL,
2612d712	279	16 => PCI_AD(0),
	280	17 => PCI_AD(1),
	281	18 => PCI_AD(2),
	282	19 => PCI_AD(3),
	283	20 => PCI_AD(4),
	284	21 => PCI_AD(5),
	285	22 => PCI_AD(6),
	286	23 => PCI_AD(7),
	287	27 => PCI_FRAMEn,
	288	28 => PCI_CBEn(0),
	289	29 => PCI_CBEn(1),
	290	30 => PCI_CBEn(2),
	291	31 => PCI_CBEn(3),
	292	others => '0');
696ded12	293
2612d712	294	data(0) <= watch_PCI_INTAn;
	295	data(1) <= R_EFn;
	296	data(2) <= R_HFn;
	297	data(3) <= R_FFn;
	298	data(4) <= R_FIFO_READn;
	299	data(5) <= R_FIFO_RESETn;
	300	data(6) <= R_FIFO_RTn;
	301	data(7) <= R_FIFO_WRITEn;
	302	data(8) <= S_EFn;
	303	data(9) <= S_HFn;
	304	data(10) <= S_FFn;
	305	data(11) <= S_FIFO_READn;
	306	data(12) <= S_FIFO_RESETn;
	307	data(13) <= S_FIFO_RTn;
	308	data(14) <= S_FIFO_WRITEn;
	309	data(15) <= SERIAL_IN;
	310	data(16) <= SPC_RDY_IN;
	311	data(17) <= SERIAL_OUT;
	312	data(18) <= SPC_RDY_OUT;
	313	data(26 downto 19) <= S_FIFO_Q_OUT;
	314	data(34 downto 27) <= R_FIFO_Q_OUT;
	315	data(66 downto 35) <= PCI_AD(31 downto 0);
	316	data(70 downto 67) <= PCI_CBEn(3 downto 0);
	317	data(71) <= PCI_FRAMEn;
	318	data(72) <= PCI_IDSEL;
	319	PCI_TRDYn <= watch_PCI_TRDYn;
	320	data(73) <= watch_PCI_TRDYn;
	321	data(74) <= PCI_IRDYn;
	322	PCI_STOPn <= watch_PCI_STOPn;
	323	data(75) <= watch_PCI_STOPn;
	324	PCI_SERRn <= watch_PCI_SERRn;
	325	data(76) <= watch_PCI_SERRn;
	326	PCI_PERRn <= watch_PCI_PERRn;
	327	data(77) <= watch_PCI_PERRn;
	328	PCI_REQn <= watch_PCI_REQn;
	329	data(78) <= watch_PCI_REQn;
	330	data(79) <= PCI_GNTn;
696ded12	331
2612d712	332	I19 : MESS_1_TB
	333	Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
	334	PCI_IDSEL=>PCI_IDSEL,
	335	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
	336	TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
	337	TB_PCI_IDSEL=>TB_IDSEL );
	338	I18 : VEN_REV_ID
	339	Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
	340	VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
	341	I16 : INTERRUPT
	342	Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
	343	INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
	344	INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
	345	INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
	346	INT_RES(7 downto 0)=>AD_REG(7 downto 0),
	347	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
	348	READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
	349	TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
	350	TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
	351	INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
	352	I14 : FIFO_CONTROL
	353	Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
	354	FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
	355	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
	356	R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
	357	RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
	358	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
	359	S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
	360	SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
	361	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
	362	R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
	363	R_FIFO_READn=>R_FIFO_READn,
	364	R_FIFO_RESETn=>R_FIFO_RESETn,
	365	R_FIFO_RETRANSMITn=>R_FIFO_RTn,
	366	R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
	367	S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
	368	S_FIFO_RESETn=>S_FIFO_RESETn,
	369	S_FIFO_RETRANSMITn=>S_FIFO_RTn,
	370	S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
	371	SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
	372	SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
	373	I1 : PCI_TOP
	374	Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
	375	INT_REG(7 downto 0)=>INT_REG(7 downto 0),
	376	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
	377	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
	378	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
	379	PCI_RSTn=>PCI_RSTn,
	380	R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
	381	REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
	382	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
	383	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
	384	PCI_PAR=>PCI_PAR,
	385	AD_REG(31 downto 0)=>AD_REG(31 downto 0),
	386	DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
	387	PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
	388	PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
	389	PCI_TRDYn=>watch_PCI_TRDYn,
	390	READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
	391	READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
	392	READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
	393	REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
	394	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
	395	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
396	TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
397	WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
398	WRITE_XX7_6=>WRITE_XX7_6 );
696ded12	399
2612d712	400	receive_fifo : dhwk_fifo
	401	port map (
	402	clk => PCI_CLOCK,
	403	din => R_FIFO_D_IN,
	404	rd_en => not R_FIFO_READn,
	405	rst => not R_FIFO_RESETn,
	406	wr_en => not R_FIFO_WRITEn,
	407	dout => R_FIFO_Q_OUT,
	408	empty => R_EFn,
	409	full => R_FFn,
	410	prog_full => R_HFn);
696ded12	411
2612d712	412	send_fifo : dhwk_fifo
	413	port map (
	414	clk => PCI_CLOCK,
	415	din => S_FIFO_D_IN,
	416	rd_en => not S_FIFO_READn,
	417	rst => not S_FIFO_RESETn,
	418	wr_en => not S_FIFO_WRITEn,
	419	dout => S_FIFO_Q_OUT,
	420	empty => S_EFn,
	421	full => S_FFn,
	422	prog_full => S_HFn);
696ded12	423
2612d712	424	i_icon : icon
	425	port map
	426	(
cf1ee28a	427	control0 => control0,
cf1ee28a	428	control1 => control1
2612d712	429	);
696ded12	430
2612d712	431	i_ila : ila
	432	port map
	433	(
	434	control => control0,
	435	clk => PCI_CLOCK,
	436	data => data,
	437	trig0 => trig0
	438	);
cf1ee28a	439
	440	i_vio : vio
	441	port map
	442	(
	443	control => control1,
	444	async_out => vio_async_out
	445	);
696ded12	446	end SCHEMATIC;