ebba63a9 |
1 | library ieee; |
2 | |
3 | use ieee.std_logic_1164.all; |
4 | use ieee.std_logic_unsigned.all; |
5 | |
6 | entity heartbeat is |
7 | generic ( |
8 | divider : std_logic_vector(31 downto 0) := X"01F78A40" |
9 | ); |
10 | |
11 | port ( |
12 | clk_i : in std_logic; |
13 | nrst_i : in std_logic; |
14 | led2_o : out std_logic; |
15 | led3_o : out std_logic; |
16 | led4_o : out std_logic; |
17 | led5_o : out std_logic |
18 | ); |
19 | |
20 | end heartbeat; |
21 | |
22 | architecture rtl of heartbeat is |
23 | begin |
24 | |
25 | process(clk_i, nrst_i) |
26 | variable counter : std_logic_vector(31 downto 0); |
27 | variable state : std_logic := '0'; |
28 | begin |
29 | |
30 | if (clk_i'event AND clk_i = '1') then |
31 | if nrst_i = '0' then |
32 | counter := (others => '0'); |
33 | else |
34 | led5_o <= state; |
35 | led2_o <= state; |
36 | led4_o <= not state; |
37 | led3_o <= not state; |
38 | counter := counter + 1; |
39 | if counter = divider then |
40 | state := not state; |
41 | counter := (others => '0'); |
42 | end if; |
43 | end if; |
44 | end if; |
45 | end process; |
46 | end architecture; |