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[raggedstone] / ethernet / source / pci / pci_async_reset_flop.v
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40a1f26c 1//===========================================================================
2// $Id: pci_async_reset_flop.v,v 1.1 2007-03-20 17:50:56 sithglan Exp $
3//
4//////////////////////////////////////////////////////////////////////
5//// ////
6//// async_reset_flop ////
7//// ////
8//// This file is part of the general opencores effort. ////
9//// <http://www.opencores.org/cores/misc/> ////
10//// ////
11//// Module Description: ////
12//// ////
13//// Make a rising-edge triggered flop with async reset with a ////
14//// distinguished name so that it's output can be easily ////
15//// traced, because it is used for asynchronous reset of some ////
16//// flip-flops. ////
17//// ////
18//// This flop should be used instead of a regular flop for ALL ////
19//// asynchronous-reset generator flops. ////
20//// ////
21//// To Do: ////
22//// Nothing ////
23//// ////
24//// Author(s): ////
25//// - Tadej Markovic, tadej@opencores.org ////
26//// ////
27//////////////////////////////////////////////////////////////////////
28//// ////
29//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
30//// ////
31//// This source file may be used and distributed without ////
32//// restriction provided that this copyright statement is not ////
33//// removed from the file and that any derivative work contains ////
34//// the original copyright notice and the associated disclaimer. ////
35//// ////
36//// This source file is free software; you can redistribute it ////
37//// and/or modify it under the terms of the GNU Lesser General ////
38//// Public License as published by the Free Software Foundation; ////
39//// either version 2.1 of the License, or (at your option) any ////
40//// later version. ////
41//// ////
42//// This source is distributed in the hope that it will be ////
43//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
44//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
45//// PURPOSE. See the GNU Lesser General Public License for more ////
46//// details. ////
47//// ////
48//// You should have received a copy of the GNU Lesser General ////
49//// Public License along with this source; if not, download it ////
50//// from <http://www.opencores.org/lgpl.shtml> ////
51//// ////
52//////////////////////////////////////////////////////////////////////
53//
54// CVS Revision History
55//
56// $Log: pci_async_reset_flop.v,v $
57// Revision 1.1 2007-03-20 17:50:56 sithglan
58// add shit
59//
60// Revision 1.1 2003/01/27 16:49:31 mihad
61// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
62//
63// Revision 1.3 2002/08/14 16:44:19 mihad
64// Include statement was enclosed in synosys translate off/on directive - repaired
65//
66// Revision 1.2 2002/02/25 15:15:43 mihad
67// Added include statement that was missing and causing errors
68//
69// Revision 1.1 2002/02/01 14:43:31 mihad
70// *** empty log message ***
71//
72//
73//
74
75// synopsys translate_off
76`include "timescale.v"
77// synopsys translate_on
78
79`include "pci_constants.v"
80
81module pci_async_reset_flop (
82 data_in, clk_in, async_reset_data_out, reset_in
83);
84
85input data_in;
86input clk_in;
87output async_reset_data_out;
88input reset_in;
89
90reg async_reset_data_out;
91
92always @(posedge clk_in or posedge reset_in)
93begin
94 if (reset_in)
95 begin
96 async_reset_data_out <= #`FF_DELAY 1'b0;
97 end
98 else
99 begin
100 async_reset_data_out <= #`FF_DELAY data_in;
101 end
102end
103
104endmodule
105
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