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40a1f26c 1//////////////////////////////////////////////////////////////////////
2//// ////
3//// File name "pci_io_mux.v" ////
4//// ////
5//// This file is part of the "PCI bridge" project ////
6//// http://www.opencores.org/cores/pci/ ////
7//// ////
8//// Author(s): ////
9//// - Miha Dolenc (mihad@opencores.org) ////
10//// ////
11//// All additional information is avaliable in the README ////
12//// file. ////
13//// ////
14//// ////
15//////////////////////////////////////////////////////////////////////
16//// ////
17//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18//// ////
19//// This source file may be used and distributed without ////
20//// restriction provided that this copyright statement is not ////
21//// removed from the file and that any derivative work contains ////
22//// the original copyright notice and the associated disclaimer. ////
23//// ////
24//// This source file is free software; you can redistribute it ////
25//// and/or modify it under the terms of the GNU Lesser General ////
26//// Public License as published by the Free Software Foundation; ////
27//// either version 2.1 of the License, or (at your option) any ////
28//// later version. ////
29//// ////
30//// This source is distributed in the hope that it will be ////
31//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33//// PURPOSE. See the GNU Lesser General Public License for more ////
34//// details. ////
35//// ////
36//// You should have received a copy of the GNU Lesser General ////
37//// Public License along with this source; if not, download it ////
38//// from http://www.opencores.org/lgpl.shtml ////
39//// ////
40//////////////////////////////////////////////////////////////////////
41//
42// CVS Revision History
43//
44// $Log: pci_io_mux.v,v $
45// Revision 1.1 2007-03-20 17:50:56 sithglan
46// add shit
47//
48// Revision 1.5 2003/12/19 11:11:30 mihad
49// Compact PCI Hot Swap support added.
50// New testcases added.
51// Specification updated.
52// Test application changed to support WB B3 cycles.
53//
54// Revision 1.4 2003/01/27 16:49:31 mihad
55// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
56//
57// Revision 1.3 2002/02/01 15:25:12 mihad
58// Repaired a few bugs, updated specification, added test bench files and design document
59//
60// Revision 1.2 2001/10/05 08:14:29 mihad
61// Updated all files with inclusion of timescale file for simulation purposes.
62//
63// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
64// New project directory structure
65//
66//
67
68// this module instantiates output flip flops for PCI interface and
69// some fanout downsizing logic because of heavily constrained PCI signals
70
71// synopsys translate_off
72`include "timescale.v"
73// synopsys translate_on
74
75module pci_io_mux
76(
77 reset_in,
78 clk_in,
79 frame_in,
80 frame_en_in,
81 frame_load_in,
82 irdy_in,
83 irdy_en_in,
84 devsel_in,
85 devsel_en_in,
86 trdy_in,
87 trdy_en_in,
88 stop_in,
89 stop_en_in,
90 master_load_in,
91 master_load_on_transfer_in,
92 target_load_in,
93 target_load_on_transfer_in,
94 cbe_in,
95 cbe_en_in,
96 mas_ad_in,
97 tar_ad_in,
98
99 par_in,
100 par_en_in,
101 perr_in,
102 perr_en_in,
103 serr_in,
104 serr_en_in,
105
106 req_in,
107
108 mas_ad_en_in,
109 tar_ad_en_in,
110 tar_ad_en_reg_in,
111
112 ad_en_out,
113 frame_en_out,
114 irdy_en_out,
115 devsel_en_out,
116 trdy_en_out,
117 stop_en_out,
118 cbe_en_out,
119
120 frame_out,
121 irdy_out,
122 devsel_out,
123 trdy_out,
124 stop_out,
125 cbe_out,
126 ad_out,
127 ad_load_out,
128 ad_en_unregistered_out,
129
130 par_out,
131 par_en_out,
132 perr_out,
133 perr_en_out,
134 serr_out,
135 serr_en_out,
136
137 req_out,
138 req_en_out,
139 pci_trdy_in,
140 pci_irdy_in,
141 pci_frame_in,
142 pci_stop_in,
143
144 init_complete_in
145);
146
147input reset_in, clk_in ;
148
149input frame_in ;
150input frame_en_in ;
151input frame_load_in ;
152input irdy_in ;
153input irdy_en_in ;
154input devsel_in ;
155input devsel_en_in ;
156input trdy_in ;
157input trdy_en_in ;
158input stop_in ;
159input stop_en_in ;
160input master_load_in ;
161input target_load_in ;
162
163input [3:0] cbe_in ;
164input cbe_en_in ;
165input [31:0] mas_ad_in ;
166input [31:0] tar_ad_in ;
167
168input mas_ad_en_in ;
169input tar_ad_en_in ;
170input tar_ad_en_reg_in ;
171
172input par_in ;
173input par_en_in ;
174input perr_in ;
175input perr_en_in ;
176input serr_in ;
177input serr_en_in ;
178
179output frame_en_out ;
180output irdy_en_out ;
181output devsel_en_out ;
182output trdy_en_out ;
183output stop_en_out ;
184output [31:0] ad_en_out ;
185output [3:0] cbe_en_out ;
186
187output frame_out ;
188output irdy_out ;
189output devsel_out ;
190output trdy_out ;
191output stop_out ;
192output [3:0] cbe_out ;
193output [31:0] ad_out ;
194output ad_load_out ;
195output ad_en_unregistered_out ;
196
197output par_out ;
198output par_en_out ;
199output perr_out ;
200output perr_en_out ;
201output serr_out ;
202output serr_en_out ;
203
204input req_in ;
205
206output req_out ;
207output req_en_out ;
208
209input pci_trdy_in,
210 pci_irdy_in,
211 pci_frame_in,
212 pci_stop_in ;
213
214input master_load_on_transfer_in ;
215input target_load_on_transfer_in ;
216
217input init_complete_in ;
218
219wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
220
221wire ad_en_ctrl_low ;
222
223wire ad_en_ctrl_mlow ;
224
225wire ad_en_ctrl_mhigh ;
226
227wire ad_en_ctrl_high ;
228
229wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
230
231pci_io_mux_ad_en_crit ad_en_low_gen
232(
233 .ad_en_in (ad_enable_internal),
234 .pci_frame_in (pci_frame_in),
235 .pci_trdy_in (pci_trdy_in),
236 .pci_stop_in (pci_stop_in),
237 .ad_en_out (ad_en_ctrl_low)
238);
239
240pci_io_mux_ad_en_crit ad_en_mlow_gen
241(
242 .ad_en_in (ad_enable_internal),
243 .pci_frame_in (pci_frame_in),
244 .pci_trdy_in (pci_trdy_in),
245 .pci_stop_in (pci_stop_in),
246 .ad_en_out (ad_en_ctrl_mlow)
247);
248
249pci_io_mux_ad_en_crit ad_en_mhigh_gen
250(
251 .ad_en_in (ad_enable_internal),
252 .pci_frame_in (pci_frame_in),
253 .pci_trdy_in (pci_trdy_in),
254 .pci_stop_in (pci_stop_in),
255 .ad_en_out (ad_en_ctrl_mhigh)
256);
257
258pci_io_mux_ad_en_crit ad_en_high_gen
259(
260 .ad_en_in (ad_enable_internal),
261 .pci_frame_in (pci_frame_in),
262 .pci_trdy_in (pci_trdy_in),
263 .pci_stop_in (pci_stop_in),
264 .ad_en_out (ad_en_ctrl_high)
265);
266
267assign ad_en_unregistered_out = ad_en_ctrl_high ;
268
269wire load = master_load_in || target_load_in ;
270wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
271
272wire ad_load_ctrl_low ;
273wire ad_load_ctrl_mlow ;
274wire ad_load_ctrl_mhigh ;
275wire ad_load_ctrl_high ;
276
277assign ad_load_out = ad_load_ctrl_high ;
278
279pci_io_mux_ad_load_crit ad_load_low_gen
280(
281 .load_in(load),
282 .load_on_transfer_in(load_on_transfer),
283 .pci_irdy_in(pci_irdy_in),
284 .pci_trdy_in(pci_trdy_in),
285 .load_out(ad_load_ctrl_low)
286);
287
288pci_io_mux_ad_load_crit ad_load_mlow_gen
289(
290 .load_in(load),
291 .load_on_transfer_in(load_on_transfer),
292 .pci_irdy_in(pci_irdy_in),
293 .pci_trdy_in(pci_trdy_in),
294 .load_out(ad_load_ctrl_mlow)
295);
296
297pci_io_mux_ad_load_crit ad_load_mhigh_gen
298(
299 .load_in(load),
300 .load_on_transfer_in(load_on_transfer),
301 .pci_irdy_in(pci_irdy_in),
302 .pci_trdy_in(pci_trdy_in),
303 .load_out(ad_load_ctrl_mhigh)
304);
305
306pci_io_mux_ad_load_crit ad_load_high_gen
307(
308 .load_in(load),
309 .load_on_transfer_in(load_on_transfer),
310 .pci_irdy_in(pci_irdy_in),
311 .pci_trdy_in(pci_trdy_in),
312 .load_out(ad_load_ctrl_high)
313);
314
315pci_out_reg ad_iob0
316(
317 .reset_in ( reset_in ),
318 .clk_in ( clk_in) ,
319 .dat_en_in ( ad_load_ctrl_low ),
320 .en_en_in ( 1'b1 ),
321 .dat_in ( temp_ad[0] ) ,
322 .en_in ( ad_en_ctrl_low ) ,
323 .en_out ( ad_en_out[0] ),
324 .dat_out ( ad_out[0] )
325);
326
327pci_out_reg ad_iob1
328(
329 .reset_in ( reset_in ),
330 .clk_in ( clk_in) ,
331 .dat_en_in ( ad_load_ctrl_low ),
332 .en_en_in ( 1'b1 ),
333 .dat_in ( temp_ad[1] ) ,
334 .en_in ( ad_en_ctrl_low ) ,
335 .en_out ( ad_en_out[1] ),
336 .dat_out ( ad_out[1] )
337);
338
339pci_out_reg ad_iob2
340(
341 .reset_in ( reset_in ),
342 .clk_in ( clk_in) ,
343 .dat_en_in ( ad_load_ctrl_low ),
344 .en_en_in ( 1'b1 ),
345 .dat_in ( temp_ad[2] ) ,
346 .en_in ( ad_en_ctrl_low ) ,
347 .en_out ( ad_en_out[2] ),
348 .dat_out ( ad_out[2] )
349);
350
351pci_out_reg ad_iob3
352(
353 .reset_in ( reset_in ),
354 .clk_in ( clk_in) ,
355 .dat_en_in ( ad_load_ctrl_low ),
356 .en_en_in ( 1'b1 ),
357 .dat_in ( temp_ad[3] ) ,
358 .en_in ( ad_en_ctrl_low ) ,
359 .en_out ( ad_en_out[3] ),
360 .dat_out ( ad_out[3] )
361);
362
363pci_out_reg ad_iob4
364(
365 .reset_in ( reset_in ),
366 .clk_in ( clk_in) ,
367 .dat_en_in ( ad_load_ctrl_low ),
368 .en_en_in ( 1'b1 ),
369 .dat_in ( temp_ad[4] ) ,
370 .en_in ( ad_en_ctrl_low ) ,
371 .en_out ( ad_en_out[4] ),
372 .dat_out ( ad_out[4] )
373);
374
375pci_out_reg ad_iob5
376(
377 .reset_in ( reset_in ),
378 .clk_in ( clk_in) ,
379 .dat_en_in ( ad_load_ctrl_low ),
380 .en_en_in ( 1'b1 ),
381 .dat_in ( temp_ad[5] ) ,
382 .en_in ( ad_en_ctrl_low ) ,
383 .en_out ( ad_en_out[5] ),
384 .dat_out ( ad_out[5] )
385);
386
387pci_out_reg ad_iob6
388(
389 .reset_in ( reset_in ),
390 .clk_in ( clk_in) ,
391 .dat_en_in ( ad_load_ctrl_low ),
392 .en_en_in ( 1'b1 ),
393 .dat_in ( temp_ad[6] ) ,
394 .en_in ( ad_en_ctrl_low ) ,
395 .en_out ( ad_en_out[6] ),
396 .dat_out ( ad_out[6] )
397);
398
399pci_out_reg ad_iob7
400(
401 .reset_in ( reset_in ),
402 .clk_in ( clk_in) ,
403 .dat_en_in ( ad_load_ctrl_low ),
404 .en_en_in ( 1'b1 ),
405 .dat_in ( temp_ad[7] ) ,
406 .en_in ( ad_en_ctrl_low ) ,
407 .en_out ( ad_en_out[7] ),
408 .dat_out ( ad_out[7] )
409);
410
411pci_out_reg ad_iob8
412(
413 .reset_in ( reset_in ),
414 .clk_in ( clk_in) ,
415 .dat_en_in ( ad_load_ctrl_mlow ),
416 .en_en_in ( 1'b1 ),
417 .dat_in ( temp_ad[8] ) ,
418 .en_in ( ad_en_ctrl_mlow ) ,
419 .en_out ( ad_en_out[8] ),
420 .dat_out ( ad_out[8] )
421);
422
423pci_out_reg ad_iob9
424(
425 .reset_in ( reset_in ),
426 .clk_in ( clk_in) ,
427 .dat_en_in ( ad_load_ctrl_mlow ),
428 .en_en_in ( 1'b1 ),
429 .dat_in ( temp_ad[9] ) ,
430 .en_in ( ad_en_ctrl_mlow ) ,
431 .en_out ( ad_en_out[9] ),
432 .dat_out ( ad_out[9] )
433);
434
435pci_out_reg ad_iob10
436(
437 .reset_in ( reset_in ),
438 .clk_in ( clk_in) ,
439 .dat_en_in ( ad_load_ctrl_mlow ),
440 .en_en_in ( 1'b1 ),
441 .dat_in ( temp_ad[10] ) ,
442 .en_in ( ad_en_ctrl_mlow ) ,
443 .en_out ( ad_en_out[10] ),
444 .dat_out ( ad_out[10] )
445);
446
447pci_out_reg ad_iob11
448(
449 .reset_in ( reset_in ),
450 .clk_in ( clk_in) ,
451 .dat_en_in ( ad_load_ctrl_mlow ),
452 .en_en_in ( 1'b1 ),
453 .dat_in ( temp_ad[11] ) ,
454 .en_in ( ad_en_ctrl_mlow ) ,
455 .en_out ( ad_en_out[11] ),
456 .dat_out ( ad_out[11] )
457);
458
459pci_out_reg ad_iob12
460(
461 .reset_in ( reset_in ),
462 .clk_in ( clk_in) ,
463 .dat_en_in ( ad_load_ctrl_mlow ),
464 .en_en_in ( 1'b1 ),
465 .dat_in ( temp_ad[12] ) ,
466 .en_in ( ad_en_ctrl_mlow ) ,
467 .en_out ( ad_en_out[12] ),
468 .dat_out ( ad_out[12] )
469);
470
471pci_out_reg ad_iob13
472(
473 .reset_in ( reset_in ),
474 .clk_in ( clk_in) ,
475 .dat_en_in ( ad_load_ctrl_mlow ),
476 .en_en_in ( 1'b1 ),
477 .dat_in ( temp_ad[13] ) ,
478 .en_in ( ad_en_ctrl_mlow ) ,
479 .en_out ( ad_en_out[13] ),
480 .dat_out ( ad_out[13] )
481);
482
483pci_out_reg ad_iob14
484(
485 .reset_in ( reset_in ),
486 .clk_in ( clk_in) ,
487 .dat_en_in ( ad_load_ctrl_mlow ),
488 .en_en_in ( 1'b1 ),
489 .dat_in ( temp_ad[14] ) ,
490 .en_in ( ad_en_ctrl_mlow ) ,
491 .en_out ( ad_en_out[14] ),
492 .dat_out ( ad_out[14] )
493);
494
495pci_out_reg ad_iob15
496(
497 .reset_in ( reset_in ),
498 .clk_in ( clk_in) ,
499 .dat_en_in ( ad_load_ctrl_mlow ),
500 .en_en_in ( 1'b1 ),
501 .dat_in ( temp_ad[15] ) ,
502 .en_in ( ad_en_ctrl_mlow ) ,
503 .en_out ( ad_en_out[15] ),
504 .dat_out ( ad_out[15] )
505);
506
507pci_out_reg ad_iob16
508(
509 .reset_in ( reset_in ),
510 .clk_in ( clk_in) ,
511 .dat_en_in ( ad_load_ctrl_mhigh ),
512 .en_en_in ( 1'b1 ),
513 .dat_in ( temp_ad[16] ) ,
514 .en_in ( ad_en_ctrl_mhigh ) ,
515 .en_out ( ad_en_out[16] ),
516 .dat_out ( ad_out[16] )
517);
518
519pci_out_reg ad_iob17
520(
521 .reset_in ( reset_in ),
522 .clk_in ( clk_in) ,
523 .dat_en_in ( ad_load_ctrl_mhigh ),
524 .en_en_in ( 1'b1 ),
525 .dat_in ( temp_ad[17] ) ,
526 .en_in ( ad_en_ctrl_mhigh ) ,
527 .en_out ( ad_en_out[17] ),
528 .dat_out ( ad_out[17] )
529);
530
531pci_out_reg ad_iob18
532(
533 .reset_in ( reset_in ),
534 .clk_in ( clk_in) ,
535 .dat_en_in ( ad_load_ctrl_mhigh ),
536 .en_en_in ( 1'b1 ),
537 .dat_in ( temp_ad[18] ) ,
538 .en_in ( ad_en_ctrl_mhigh ) ,
539 .en_out ( ad_en_out[18] ),
540 .dat_out ( ad_out[18] )
541);
542
543pci_out_reg ad_iob19
544(
545 .reset_in ( reset_in ),
546 .clk_in ( clk_in) ,
547 .dat_en_in ( ad_load_ctrl_mhigh ),
548 .en_en_in ( 1'b1 ),
549 .dat_in ( temp_ad[19] ) ,
550 .en_in ( ad_en_ctrl_mhigh ) ,
551 .en_out ( ad_en_out[19] ),
552 .dat_out ( ad_out[19] )
553);
554
555pci_out_reg ad_iob20
556(
557 .reset_in ( reset_in ),
558 .clk_in ( clk_in) ,
559 .dat_en_in ( ad_load_ctrl_mhigh ),
560 .en_en_in ( 1'b1 ),
561 .dat_in ( temp_ad[20] ) ,
562 .en_in ( ad_en_ctrl_mhigh ) ,
563 .en_out ( ad_en_out[20] ),
564 .dat_out ( ad_out[20] )
565);
566
567pci_out_reg ad_iob21
568(
569 .reset_in ( reset_in ),
570 .clk_in ( clk_in) ,
571 .dat_en_in ( ad_load_ctrl_mhigh ),
572 .en_en_in ( 1'b1 ),
573 .dat_in ( temp_ad[21] ) ,
574 .en_in ( ad_en_ctrl_mhigh ) ,
575 .en_out ( ad_en_out[21] ),
576 .dat_out ( ad_out[21] )
577);
578
579pci_out_reg ad_iob22
580(
581 .reset_in ( reset_in ),
582 .clk_in ( clk_in) ,
583 .dat_en_in ( ad_load_ctrl_mhigh ),
584 .en_en_in ( 1'b1 ),
585 .dat_in ( temp_ad[22] ) ,
586 .en_in ( ad_en_ctrl_mhigh ) ,
587 .en_out ( ad_en_out[22] ),
588 .dat_out ( ad_out[22] )
589);
590
591pci_out_reg ad_iob23
592(
593 .reset_in ( reset_in ),
594 .clk_in ( clk_in) ,
595 .dat_en_in ( ad_load_ctrl_mhigh ),
596 .en_en_in ( 1'b1 ),
597 .dat_in ( temp_ad[23] ) ,
598 .en_in ( ad_en_ctrl_mhigh ) ,
599 .en_out ( ad_en_out[23] ),
600 .dat_out ( ad_out[23] )
601);
602
603pci_out_reg ad_iob24
604(
605 .reset_in ( reset_in ),
606 .clk_in ( clk_in) ,
607 .dat_en_in ( ad_load_ctrl_high ),
608 .en_en_in ( 1'b1 ),
609 .dat_in ( temp_ad[24] ) ,
610 .en_in ( ad_en_ctrl_high ) ,
611 .en_out ( ad_en_out[24] ),
612 .dat_out ( ad_out[24] )
613);
614
615pci_out_reg ad_iob25
616(
617 .reset_in ( reset_in ),
618 .clk_in ( clk_in) ,
619 .dat_en_in ( ad_load_ctrl_high ),
620 .en_en_in ( 1'b1 ),
621 .dat_in ( temp_ad[25] ) ,
622 .en_in ( ad_en_ctrl_high ) ,
623 .en_out ( ad_en_out[25] ),
624 .dat_out ( ad_out[25] )
625);
626
627pci_out_reg ad_iob26
628(
629 .reset_in ( reset_in ),
630 .clk_in ( clk_in) ,
631 .dat_en_in ( ad_load_ctrl_high ),
632 .en_en_in ( 1'b1 ),
633 .dat_in ( temp_ad[26] ) ,
634 .en_in ( ad_en_ctrl_high ) ,
635 .en_out ( ad_en_out[26] ),
636 .dat_out ( ad_out[26] )
637);
638
639pci_out_reg ad_iob27
640(
641 .reset_in ( reset_in ),
642 .clk_in ( clk_in) ,
643 .dat_en_in ( ad_load_ctrl_high ),
644 .en_en_in ( 1'b1 ),
645 .dat_in ( temp_ad[27] ) ,
646 .en_in ( ad_en_ctrl_high ) ,
647 .en_out ( ad_en_out[27] ),
648 .dat_out ( ad_out[27] )
649);
650
651pci_out_reg ad_iob28
652(
653 .reset_in ( reset_in ),
654 .clk_in ( clk_in) ,
655 .dat_en_in ( ad_load_ctrl_high ),
656 .en_en_in ( 1'b1 ),
657 .dat_in ( temp_ad[28] ) ,
658 .en_in ( ad_en_ctrl_high ) ,
659 .en_out ( ad_en_out[28] ),
660 .dat_out ( ad_out[28] )
661);
662
663pci_out_reg ad_iob29
664(
665 .reset_in ( reset_in ),
666 .clk_in ( clk_in) ,
667 .dat_en_in ( ad_load_ctrl_high ),
668 .en_en_in ( 1'b1 ),
669 .dat_in ( temp_ad[29] ) ,
670 .en_in ( ad_en_ctrl_high ) ,
671 .en_out ( ad_en_out[29] ),
672 .dat_out ( ad_out[29] )
673);
674
675pci_out_reg ad_iob30
676(
677 .reset_in ( reset_in ),
678 .clk_in ( clk_in) ,
679 .dat_en_in ( ad_load_ctrl_high ),
680 .en_en_in ( 1'b1 ),
681 .dat_in ( temp_ad[30] ) ,
682 .en_in ( ad_en_ctrl_high ) ,
683 .en_out ( ad_en_out[30] ),
684 .dat_out ( ad_out[30] )
685);
686
687pci_out_reg ad_iob31
688(
689 .reset_in ( reset_in ),
690 .clk_in ( clk_in) ,
691 .dat_en_in ( ad_load_ctrl_high ),
692 .en_en_in ( 1'b1 ),
693 .dat_in ( temp_ad[31] ) ,
694 .en_in ( ad_en_ctrl_high ) ,
695 .en_out ( ad_en_out[31] ),
696 .dat_out ( ad_out[31] )
697);
698
699wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
700wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ;
701
702pci_out_reg cbe_iob0
703(
704 .reset_in ( reset_in ),
705 .clk_in ( clk_in) ,
706 .dat_en_in ( cbe_load_ctrl[0] ),
707 .en_en_in ( 1'b1 ),
708 .dat_in ( cbe_in[0] ) ,
709 .en_in ( cbe_en_ctrl[0] ) ,
710 .en_out ( cbe_en_out[0] ),
711 .dat_out ( cbe_out[0] )
712);
713
714pci_out_reg cbe_iob1
715(
716 .reset_in ( reset_in ),
717 .clk_in ( clk_in) ,
718 .dat_en_in ( cbe_load_ctrl[1] ),
719 .en_en_in ( 1'b1 ),
720 .dat_in ( cbe_in[1] ) ,
721 .en_in ( cbe_en_ctrl[1] ) ,
722 .en_out ( cbe_en_out[1] ),
723 .dat_out ( cbe_out[1] )
724);
725
726pci_out_reg cbe_iob2
727(
728 .reset_in ( reset_in ),
729 .clk_in ( clk_in) ,
730 .dat_en_in ( cbe_load_ctrl[2] ),
731 .en_en_in ( 1'b1 ),
732 .dat_in ( cbe_in[2] ) ,
733 .en_in ( cbe_en_ctrl[2] ) ,
734 .en_out ( cbe_en_out[2] ),
735 .dat_out ( cbe_out[2] )
736);
737
738pci_out_reg cbe_iob3
739(
740 .reset_in ( reset_in ),
741 .clk_in ( clk_in) ,
742 .dat_en_in ( cbe_load_ctrl[3] ),
743 .en_en_in ( 1'b1 ),
744 .dat_in ( cbe_in[3] ) ,
745 .en_in ( cbe_en_ctrl[3] ) ,
746 .en_out ( cbe_en_out[3] ),
747 .dat_out ( cbe_out[3] )
748);
749
750pci_out_reg frame_iob
751(
752 .reset_in ( reset_in ),
753 .clk_in ( clk_in) ,
754 .dat_en_in ( frame_load_in ),
755 .en_en_in ( 1'b1 ),
756 .dat_in ( frame_in ) ,
757 .en_in ( frame_en_in ) ,
758 .en_out ( frame_en_out ),
759 .dat_out ( frame_out )
760);
761
762pci_out_reg irdy_iob
763(
764 .reset_in ( reset_in ),
765 .clk_in ( clk_in) ,
766 .dat_en_in ( 1'b1 ),
767 .en_en_in ( 1'b1 ),
768 .dat_in ( irdy_in ) ,
769 .en_in ( irdy_en_in ) ,
770 .en_out ( irdy_en_out ),
771 .dat_out ( irdy_out )
772);
773
774pci_out_reg trdy_iob
775(
776 .reset_in ( reset_in ),
777 .clk_in ( clk_in) ,
778 .dat_en_in ( 1'b1 ),
779 .en_en_in ( 1'b1 ),
780 .dat_in ( trdy_in ) ,
781 .en_in ( trdy_en_in ) ,
782 .en_out ( trdy_en_out ),
783 .dat_out ( trdy_out )
784);
785
786pci_out_reg stop_iob
787(
788 .reset_in ( reset_in ),
789 .clk_in ( clk_in) ,
790 .dat_en_in ( 1'b1 ),
791 .en_en_in ( 1'b1 ),
792 .dat_in ( stop_in ) ,
793 .en_in ( stop_en_in ) ,
794 .en_out ( stop_en_out ),
795 .dat_out ( stop_out )
796);
797
798pci_out_reg devsel_iob
799(
800 .reset_in ( reset_in ),
801 .clk_in ( clk_in) ,
802 .dat_en_in ( 1'b1 ),
803 .en_en_in ( 1'b1 ),
804 .dat_in ( devsel_in ) ,
805 .en_in ( devsel_en_in ) ,
806 .en_out ( devsel_en_out ),
807 .dat_out ( devsel_out )
808);
809
810pci_out_reg par_iob
811(
812 .reset_in ( reset_in ),
813 .clk_in ( clk_in) ,
814 .dat_en_in ( 1'b1 ),
815 .en_en_in ( 1'b1 ),
816 .dat_in ( par_in ) ,
817 .en_in ( par_en_in ) ,
818 .en_out ( par_en_out ),
819 .dat_out ( par_out )
820);
821
822pci_out_reg perr_iob
823(
824 .reset_in ( reset_in ),
825 .clk_in ( clk_in) ,
826 .dat_en_in ( 1'b1 ),
827 .en_en_in ( 1'b1 ),
828 .dat_in ( perr_in ) ,
829 .en_in ( perr_en_in ) ,
830 .en_out ( perr_en_out ),
831 .dat_out ( perr_out )
832);
833
834pci_out_reg serr_iob
835(
836 .reset_in ( reset_in ),
837 .clk_in ( clk_in) ,
838 .dat_en_in ( 1'b1 ),
839 .en_en_in ( 1'b1 ),
840 .dat_in ( serr_in ) ,
841 .en_in ( serr_en_in ) ,
842 .en_out ( serr_en_out ),
843 .dat_out ( serr_out )
844);
845
846pci_out_reg req_iob
847(
848 .reset_in ( reset_in ),
849 .clk_in ( clk_in) ,
850 .dat_en_in ( 1'b1 ),
851 .en_en_in ( 1'b1 ),
852 .dat_in ( req_in ) ,
853 .en_in ( init_complete_in ) ,
854 .en_out ( req_en_out ),
855 .dat_out ( req_out )
856);
857
858endmodule
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