| 40a1f26c |
1 | //=========================================================================== |
| 2 | // $Id: pci_synchronizer_flop.v,v 1.1 2007-03-20 17:50:56 sithglan Exp $ |
| 3 | // |
| 4 | ////////////////////////////////////////////////////////////////////// |
| 5 | //// //// |
| 6 | //// pci_synchronizer_flop //// |
| 7 | //// //// |
| 8 | //// This file is part of the general opencores effort. //// |
| 9 | //// <http://www.opencores.org/cores/misc/> //// |
| 10 | //// //// |
| 11 | //// Module Description: //// |
| 12 | //// //// |
| 13 | //// Make a rising-edge triggered flop with async reset with a //// |
| 14 | //// distinguished name so that it can be replaced with a flop //// |
| 15 | //// which does not make X's during simulation. //// |
| 16 | //// //// |
| 17 | //// This flop should be used instead of a regular flop for ALL //// |
| 18 | //// cross-clock-domain flops. Manually instantiating this //// |
| 19 | //// flop for all signals which must NEVER go to 1'bX during //// |
| 20 | //// simulation will make it possible for the user to //// |
| 21 | //// substitute a simulation model which does NOT have setup //// |
| 22 | //// and hold checks. //// |
| 23 | //// //// |
| 24 | //// If a target device library has a component which is //// |
| 25 | //// especially well suited to perform this function, it should //// |
| 26 | //// be instantiated by name in this file. Otherwise, the //// |
| 27 | //// behaviorial version of this module will be used. //// |
| 28 | //// //// |
| 29 | //// To Do: //// |
| 30 | //// Nothing //// |
| 31 | //// //// |
| 32 | //// Author(s): //// |
| 33 | //// - anynomous //// |
| 34 | //// //// |
| 35 | ////////////////////////////////////////////////////////////////////// |
| 36 | //// //// |
| 37 | //// Copyright (C) 2001 Authors and OPENCORES.ORG //// |
| 38 | //// //// |
| 39 | //// This source file may be used and distributed without //// |
| 40 | //// restriction provided that this copyright statement is not //// |
| 41 | //// removed from the file and that any derivative work contains //// |
| 42 | //// the original copyright notice and the associated disclaimer. //// |
| 43 | //// //// |
| 44 | //// This source file is free software; you can redistribute it //// |
| 45 | //// and/or modify it under the terms of the GNU Lesser General //// |
| 46 | //// Public License as published by the Free Software Foundation; //// |
| 47 | //// either version 2.1 of the License, or (at your option) any //// |
| 48 | //// later version. //// |
| 49 | //// //// |
| 50 | //// This source is distributed in the hope that it will be //// |
| 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
| 54 | //// details. //// |
| 55 | //// //// |
| 56 | //// You should have received a copy of the GNU Lesser General //// |
| 57 | //// Public License along with this source; if not, download it //// |
| 58 | //// from <http://www.opencores.org/lgpl.shtml> //// |
| 59 | //// //// |
| 60 | ////////////////////////////////////////////////////////////////////// |
| 61 | // |
| 62 | // CVS Revision History |
| 63 | // |
| 64 | // $Log: pci_synchronizer_flop.v,v $ |
| 65 | // Revision 1.1 2007-03-20 17:50:56 sithglan |
| 66 | // add shit |
| 67 | // |
| 68 | // Revision 1.1 2003/08/14 13:08:58 simons |
| 69 | // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. |
| 70 | // |
| 71 | // |
| 72 | |
| 73 | // synopsys translate_off |
| 74 | `include "timescale.v" |
| 75 | // synopsys translate_on |
| 76 | |
| 77 | // If the vendor has a flop which is particularly good at settling out of |
| 78 | // metastability, it should be used here. |
| 79 | module pci_synchronizer_flop ( |
| 80 | data_in, clk_out, sync_data_out, async_reset |
| 81 | ); |
| 82 | parameter width = 1 ; |
| 83 | parameter reset_val = 0 ; |
| 84 | |
| 85 | input [width-1:0] data_in; |
| 86 | input clk_out; |
| 87 | output [width-1:0] sync_data_out; |
| 88 | input async_reset; |
| 89 | |
| 90 | reg [width-1:0] sync_data_out; |
| 91 | |
| 92 | always @(posedge clk_out or posedge async_reset) |
| 93 | begin |
| 94 | if (async_reset == 1'b1) |
| 95 | begin |
| 96 | sync_data_out <= reset_val; |
| 97 | end |
| 98 | else |
| 99 | begin |
| 100 | // In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ. |
| 101 | // This should NEVER go to 1'bX due to setup or hold violations. |
| 102 | sync_data_out <= data_in; |
| 103 | end |
| 104 | end |
| 105 | endmodule |
| 106 | |
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