]cvsignore and chipscope file for EDK project

[raggedstone] / xps / raggedstone.mhs

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Thu Mar 22 21:42:23 2007
# Target Board:  Custom
# Family:	 spartan3
# Device:	 xc3s1500
# Package:	 fg456
# Speed Grade:	 -4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :  64 KB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
 PORT RS232foff = net_vcc, DIR = O
 PORT LED_out = GPIO_LED_out, VEC = [0:3], DIR = O
 PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
 PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
 PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
 PORT MEM_FLASH_OE = FLASH_OEN, DIR = O, VEC = [0:0]
 PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
 PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
 PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.b
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_FSL_DATA_SIZE = 32
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 0
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007FFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007FFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 50000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 20.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDS
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_d_out = GPIO_LED_out
END

BEGIN opb_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 8
 PARAMETER C_MEM0_WIDTH = 8
 PARAMETER C_TCEDV_PS_MEM_0 = 70000
 PARAMETER C_TAVDV_PS_MEM_0 = 70000
 PARAMETER C_THZCE_PS_MEM_0 = 25000
 PARAMETER C_TWC_PS_MEM_0 = 110000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 15000
 PARAMETER C_OPB_CLK_PERIOD_PS = 20000
 PARAMETER C_THZOE_PS_MEM_0 = 25000
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_BASEADDR = 0x20000000
 PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 0
 BUS_INTERFACE SOPB = mb_opb
 PORT Mem_A = FLASH_ADDR_split
 PORT Mem_CEN = FLASH_CEN
 PORT Mem_OEN = FLASH_OEN
 PORT Mem_WEN = FLASH_WEN
 PORT Mem_DQ = FLASH_DQ
END

BEGIN opb_gpio
 PARAMETER INSTANCE = SEVENSEG
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 13
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_d_out = GPIO_7SEG_OUT
END

BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.01.a
 PORT control0 = ila_control0
END

BEGIN chipscope_ila
 PARAMETER INSTANCE = chipscope_ila_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_NUM_DATA_SAMPLES = 1024
 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 19
 PARAMETER C_TRIG1_UNITS = 1
 PARAMETER C_TRIG2_UNITS = 1
 PORT CHIPSCOPE_ILA_CONTROL = ila_control0
 PORT CLK = sys_clk_s
 PORT TRIG0 = FLASH_ADDR
END

BEGIN util_bus_split
 PARAMETER INSTANCE = flash_split
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_SPLIT = 13
 PORT Sig = FLASH_ADDR_split
 PORT Out2 = FLASH_ADDR
END