| | 1 | -- J.STELZNER\r |
| | 2 | -- INFORMATIK-3 LABOR\r |
| | 3 | -- 23.08.2006\r |
| | 4 | -- File: FLAG_BUS.VHD\r |
| | 5 | \r |
| | 6 | library IEEE;\r |
| | 7 | use IEEE.std_logic_1164.all;\r |
| | 8 | \r |
| | 9 | entity FLAG_BUS is\r |
| | 10 | port\r |
| | 11 | (\r |
| | 12 | PCI_CLOCK :in std_logic;\r |
| | 13 | KONS_1 :in std_logic;\r |
| | 14 | FLAG_IN_0 :in std_logic;\r |
| | 15 | R_EFn :in std_logic;\r |
| | 16 | R_HFn :in std_logic;\r |
| | 17 | R_FFn :in std_logic;\r |
| | 18 | FLAG_IN_4 :in std_logic;\r |
| | 19 | S_EFn :in std_logic;\r |
| | 20 | S_HFn :in std_logic;\r |
| | 21 | S_FFn :in std_logic;\r |
| | 22 | HOLD :in std_logic;\r |
| | 23 | SYNC_FLAG :out std_logic_vector (7 downto 0)\r |
| | 24 | ); \r |
| | 25 | end entity FLAG_BUS;\r |
| | 26 | \r |
| | 27 | architecture FLAG_BUS_DESIGN of FLAG_BUS is\r |
| | 28 | \r |
| | 29 | \r |
| | 30 | signal FF1_S_EFn :std_logic; \r |
| | 31 | signal FF1_S_HFn :std_logic;\r |
| | 32 | signal FF1_S_FFn :std_logic;\r |
| | 33 | signal FF1_R_EFn :std_logic;\r |
| | 34 | signal FF1_R_HFn :std_logic;\r |
| | 35 | signal FF1_R_FFn :std_logic;\r |
| | 36 | \r |
| | 37 | signal FF2_S_EFn :std_logic; \r |
| | 38 | signal FF2_S_HFn :std_logic;\r |
| | 39 | signal FF2_S_FFn :std_logic;\r |
| | 40 | signal FF2_R_EFn :std_logic;\r |
| | 41 | signal FF2_R_HFn :std_logic;\r |
| | 42 | signal FF2_R_FFn :std_logic;\r |
| | 43 | \r |
| | 44 | begin\r |
| | 45 | \r |
| | 46 | \r |
| | 47 | process (PCI_CLOCK) \r |
| | 48 | begin \r |
| | 49 | if (PCI_CLOCK'event and PCI_CLOCK = '1') then \r |
| | 50 | \r |
| | 51 | FF1_S_EFn <= not S_EFn;\r |
| | 52 | FF1_S_HFn <= not S_HFn;\r |
| | 53 | FF1_S_FFn <= not S_FFn;\r |
| | 54 | FF1_R_EFn <= not R_EFn;\r |
| | 55 | FF1_R_HFn <= not R_HFn;\r |
| | 56 | FF1_R_FFn <= not R_FFn;\r |
| | 57 | \r |
| | 58 | end if;\r |
| | 59 | end process; \r |
| | 60 | \r |
| | 61 | \r |
| | 62 | process (PCI_CLOCK) \r |
| | 63 | begin \r |
| | 64 | if (PCI_CLOCK'event and PCI_CLOCK = '1') then \r |
| | 65 | \r |
| | 66 | if HOLD = '0' then\r |
| | 67 | \r |
| | 68 | FF2_S_EFn <= FF1_S_EFn; \r |
| | 69 | FF2_S_HFn <= FF1_S_HFn;\r |
| | 70 | FF2_S_FFn <= FF1_S_FFn;\r |
| | 71 | FF2_R_EFn <= FF1_R_EFn;\r |
| | 72 | FF2_R_HFn <= FF1_R_HFn;\r |
| | 73 | FF2_R_FFn <= FF1_R_FFn;\r |
| | 74 | \r |
| | 75 | elsif HOLD = '1' then\r |
| | 76 | \r |
| | 77 | FF2_S_EFn <= FF2_S_EFn; \r |
| | 78 | FF2_S_HFn <= FF2_S_HFn;\r |
| | 79 | FF2_S_FFn <= FF2_S_FFn;\r |
| | 80 | FF2_R_EFn <= FF2_R_EFn;\r |
| | 81 | FF2_R_HFn <= FF2_R_HFn;\r |
| | 82 | FF2_R_FFn <= FF2_R_FFn;\r |
| | 83 | \r |
| | 84 | end if;\r |
| | 85 | end if;\r |
| | 86 | end process; \r |
| | 87 | \r |
| | 88 | SYNC_FLAG(0) <= FLAG_IN_0; \r |
| | 89 | SYNC_FLAG(1) <= FF2_R_EFn; \r |
| | 90 | SYNC_FLAG(2) <= FF2_R_HFn;\r |
| | 91 | SYNC_FLAG(3) <= FF2_R_FFn;\r |
| | 92 | SYNC_FLAG(4) <= FLAG_IN_4; \r |
| | 93 | SYNC_FLAG(5) <= FF2_S_EFn; \r |
| | 94 | SYNC_FLAG(6) <= FF2_S_HFn;\r |
| | 95 | SYNC_FLAG(7) <= FF2_S_FFn;\r |
| | 96 | \r |
| | 97 | end architecture FLAG_BUS_DESIGN;\r |
| | 98 | \r |
projects / raggedstone / blame_incremental