fifo

[raggedstone] / dhwk_old / source / wb_7seg.v

module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
	wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);\r
\r
	input clk_i;\r
	input nrst_i;\r
	input [24:1] wb_adr_i;\r
	output [15:0] wb_dat_o;\r
   	input [15:0] wb_dat_i;\r
	input [1:0] wb_sel_i;\r
   	input wb_we_i;\r
	input wb_stb_i;\r
	input wb_cyc_i;\r
	output wb_ack_o;\r
	output wb_err_o;\r
	output wb_int_o;\r
 	output reg [3:0] DISP_SEL;\r
	output reg [6:0] DISP_LED;\r
\r
	reg [15:0]	data_reg;\r
	reg	[6:0]	disp_cnt;\r
	reg	[3:0]	disp_data;\r
	wire	[6:0]	disp_data_led;\r
	reg	[3:0]	disp_pos;\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			data_reg <= 16'hABCD;\r
		else \r
			if (wb_stb_i && wb_we_i)\r
				data_reg <= wb_dat_i;\r
	end\r
\r
	assign wb_ack_o = wb_stb_i;\r
	assign wb_err_o = 1'b0;\r
	assign wb_int_o = 1'b0;\r
	assign wb_dat_o = data_reg;\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			disp_cnt <= 7'b0000000;\r
		else \r
			disp_cnt <= disp_cnt + 1;\r
	end\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			disp_pos <= 4'b0010;\r
		else \r
			if (disp_cnt == 7'b1111111)\r
				disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};\r
	end\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			disp_data <= 4'b0000;\r
		else \r
			case (DISP_SEL)\r
				4'b1000: disp_data <= data_reg[3:0];\r
				4'b0100: disp_data <= data_reg[7:4];\r
				4'b0010: disp_data <= data_reg[11:8];\r
				4'b0001: disp_data <= data_reg[15:12];\r
			endcase\r
	end\r
\r
	disp_dec u0 (disp_data, disp_data_led);\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			DISP_LED <= 7'b0000000;\r
		else \r
			DISP_LED <= disp_data_led;\r
	end\r
\r
	always @(posedge clk_i or negedge nrst_i)\r
	begin\r
		if (nrst_i == 0)\r
			DISP_SEL <= 0;\r
		else \r
			DISP_SEL <= disp_pos;\r
	end\r
\r
endmodule\r