WISHBONE B3

[raggedstone] / dhwk / source / pci / config_00h.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: CONFIG_00H.VHD

library IEEE;
use IEEE.std_logic_1164.all;

entity CONFIG_00H is
        port
        (
                VENDOR_ID :in std_logic_vector (15 downto 0);
                CONF_DATA_00H :out std_logic_vector (31 downto 0)
        );
end entity CONFIG_00H;

architecture CONFIG_00H_DESIGN of CONFIG_00H is

 -- PCI Configuration Space Header Addr : HEX 00 --

        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--????
        --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--????

begin

        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;

end architecture CONFIG_00H_DESIGN;