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it builds, lets ship it
[raggedstone] / heartbeat / source / top_raggedstone.vhd
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CommitLineData
1--+-------------------------------------------------------------------------------------------------+\r
2--| |\r
3--| File: top.vhd |\r
4--| |\r
5--| Components: pci32lite.vhd |\r
6--| pciwbsequ.vhd |\r
7--| pcidmux.vhd |\r
8--| pciregs.vhd |\r
9--| pcipargen.vhd |\r
10--| -- Libs -- |\r
11--| ona.vhd |\r
12--| |\r
13--| Description: RS1 PCI Demo : (TOP) Main file. |\r
14--| |\r
15--| |\r
16--| |\r
17--+-------------------------------------------------------------------------------------------------+\r
18--| |\r
19--| Revision history : |\r
20--| Date Version Author Description |\r
21--| |\r
22--| |\r
23--| To do: |\r
24--| |\r
25--+-------------------------------------------------------------------------------------------------+\r
26\r
27\r
28--+-----------------------------------------------------------------------------+\r
29--| LIBRARIES |\r
30--+-----------------------------------------------------------------------------+\r
31\r
32library ieee;\r
33use ieee.std_logic_1164.all;\r
34use ieee.std_logic_arith.all;\r
35use ieee.std_logic_unsigned.all;\r
36\r
37--+-----------------------------------------------------------------------------+\r
38--| ENTITY |\r
39--+-----------------------------------------------------------------------------+\r
40\r
41entity raggedstone is\r
42port (\r
43\r
44 -- General \r
45 PCI_CLK : in std_logic;\r
46 PCI_nRES : in std_logic;\r
47 PCI_nREQ : out std_logic;\r
48 \r
49 -- PCI target 32bits\r
50 PCI_AD : inout std_logic_vector(31 downto 0);\r
51 PCI_CBE : in std_logic_vector(3 downto 0);\r
52 PCI_PAR : out std_logic; \r
53 PCI_nFRAME : in std_logic;\r
54 PCI_nIRDY : in std_logic;\r
55 PCI_nTRDY : out std_logic;\r
56 PCI_nDEVSEL : out std_logic;\r
57 PCI_nSTOP : out std_logic;\r
58 PCI_IDSEL : in std_logic;\r
59 PCI_nPERR : out std_logic;\r
60 PCI_nSERR : out std_logic;\r
61 PCI_nINT : out std_logic;\r
62 \r
63 -- debug signals\r
64 LED3 : out std_logic;\r
65 LED2 : out std_logic;\r
66 LED4 : out std_logic;\r
67 LED5 : out std_logic;\r
68 IDE1 : out std_logic;\r
69 IDE2 : out std_logic;\r
70 IDE3 : out std_logic;\r
71 IDE4 : out std_logic\r
72\r
73);\r
74end raggedstone;\r
75\r
76\r
77--+-----------------------------------------------------------------------------+\r
78--| ARCHITECTURE |\r
79--+-----------------------------------------------------------------------------+\r
80\r
81architecture raggedstone_arch of raggedstone is\r
82\r
83\r
84--+-----------------------------------------------------------------------------+\r
85--| COMPONENTS |\r
86--+-----------------------------------------------------------------------------+\r
87\r
88component pci32tlite\r
89port (\r
90\r
91 -- General \r
92 clk33 : in std_logic;\r
93 nrst : in std_logic;\r
94 \r
95 -- PCI target 32bits\r
96 ad : inout std_logic_vector(31 downto 0);\r
97 cbe : in std_logic_vector(3 downto 0);\r
98 par : out std_logic; \r
99 frame : in std_logic;\r
100 irdy : in std_logic;\r
101 trdy : out std_logic;\r
102 devsel : out std_logic;\r
103 stop : out std_logic;\r
104 idsel : in std_logic;\r
105 perr : out std_logic;\r
106 serr : out std_logic;\r
107 intb : out std_logic;\r
108 \r
109 -- Master whisbone\r
110 wb_adr_o : out std_logic_vector(24 downto 1); \r
111 wb_dat_i : in std_logic_vector(15 downto 0);\r
112 wb_dat_o : out std_logic_vector(15 downto 0);\r
113 wb_sel_o : out std_logic_vector(1 downto 0);\r
114 wb_we_o : out std_logic;\r
115 wb_stb_o : out std_logic;\r
116 wb_cyc_o : out std_logic;\r
117 wb_ack_i : in std_logic;\r
118 wb_err_i : in std_logic;\r
119 wb_int_i : in std_logic;\r
120\r
121 -- debug signals\r
122 debug_init : out std_logic;\r
123 debug_access : out std_logic \r
124\r
125 );\r
126end component;\r
127\r
128component heartbeat\r
129port (\r
130 clk_i : in std_logic;\r
131 nrst_i : in std_logic;\r
132 led2_o : out std_logic;\r
133 led3_o : out std_logic;\r
134 led4_o : out std_logic;\r
135 led5_o : out std_logic;\r
136 led6_o : out std_logic;\r
137 led7_o : out std_logic;\r
138 led8_o : out std_logic;\r
139 led9_o : out std_logic\r
140);\r
141end component;\r
142\r
143\r
144--+-----------------------------------------------------------------------------+\r
145--| CONSTANTS |\r
146--+-----------------------------------------------------------------------------+\r
147--+-----------------------------------------------------------------------------+\r
148--| SIGNALS |\r
149--+-----------------------------------------------------------------------------+\r
150\r
151 signal wb_adr : std_logic_vector(24 downto 1); \r
152 signal wb_dat_out : std_logic_vector(15 downto 0);\r
153 signal wb_dat_in : std_logic_vector(15 downto 0);\r
154 signal wb_sel : std_logic_vector(1 downto 0);\r
155 signal wb_we : std_logic;\r
156 signal wb_stb : std_logic;\r
157 signal wb_cyc : std_logic;\r
158 signal wb_ack : std_logic;\r
159 signal wb_err : std_logic;\r
160 signal wb_int : std_logic;\r
161\r
162\r
163begin\r
164\r
165 PCI_nREQ <= '1';\r
166\r
167--+-----------------------------------------+\r
168--| PCI Target |\r
169--+-----------------------------------------+\r
170\r
171u_pci: component pci32tlite\r
172port map(\r
173 clk33 => PCI_CLK,\r
174 nrst => PCI_nRES,\r
175 ad => PCI_AD,\r
176 cbe => PCI_CBE,\r
177 par => PCI_PAR,\r
178 frame => PCI_nFRAME,\r
179 irdy => PCI_nIRDY,\r
180 trdy => PCI_nTRDY,\r
181 devsel => PCI_nDEVSEL,\r
182 stop => PCI_nSTOP,\r
183 idsel => PCI_IDSEL,\r
184 perr => PCI_nPERR,\r
185 serr => PCI_nSERR,\r
186 intb => PCI_nINT,\r
187 wb_adr_o => wb_adr, \r
188 wb_dat_i => wb_dat_out,\r
189 wb_dat_o => wb_dat_in,\r
190 wb_sel_o => wb_sel, \r
191 wb_we_o => wb_we,\r
192 wb_stb_o => wb_stb, \r
193 wb_cyc_o => wb_cyc,\r
194 wb_ack_i => wb_ack,\r
195 wb_err_i => wb_err,\r
196 wb_int_i => wb_int\r
197-- debug_init => LED3,\r
198-- debug_access => LED2\r
199 );\r
200\r
201--+-----------------------------------------+\r
202--| WB-7seg |\r
203--+-----------------------------------------+\r
204\r
205my_heartbeat: component heartbeat\r
206port map( \r
207 clk_i => PCI_CLK,\r
208 nrst_i => PCI_nRES,\r
209 led2_o => LED2,\r
210 led3_o => LED3,\r
211 led4_o => LED4,\r
212 led5_o => LED5,\r
213 led6_o => IDE1,\r
214 led7_o => IDE2,\r
215 led8_o => IDE3,\r
216 led9_o => IDE4\r
217);\r
218\r
219end raggedstone_arch;\r
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