]> cvs.zerfleddert.de Git - raggedstone/blame_incremental - dhwk_old/dhwk.prj
+= timescale
[raggedstone] / dhwk_old / dhwk.prj
... / ...
CommitLineData
1verilog work "source/sync.v"
2verilog work "source/pcidec.v"
3verilog work "source/pcidmux.v"
4
5verilog work "source/pciwbsequ.v"
6verilog work "source/pcipargen.v"
7
8vhdl work "source/pciwbsequ.vhd"
9vhdl work "source/pfs.vhd"
10vhdl work "source/new_pciregs.vhd"
11vhdl work "source/pcipargen.vhd"
12vhdl work "source/new_pci32tlite.vhd"
13vhdl work "source/top_dhwk.vhd"
14vhdl work "source/heartbeat.vhd"
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