cvs.zerfleddert.de Git - raggedstone/blame_incremental

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Commit	Line	Data
	1	-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007\r
	2	\r
	3	--LIBRARY vanmacro;\r
	4	--USE vanmacro.components.ALL;\r
	5	LIBRARY ieee;\r
	6	--LIBRARY generics;\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	--USE generics.components.ALL;\r
	10	\r
	11	entity PARITY is\r
	12	Port ( OE_PCI_PAR : In std_logic;\r
	13	OE_PCI_PERR : In std_logic;\r
	14	PA_ER_RE : In std_logic;\r
	15	PAR_IN : In std_logic_vector (35 downto 0);\r
	16	PAR_REG : In std_logic;\r
	17	PCI_CLOCK : In std_logic;\r
	18	PCI_RSTn : In std_logic;\r
	19	PERR_CHECK : In std_logic;\r
	20	SERR_CHECK : In std_logic;\r
	21	SERR_ENA : In std_logic;\r
	22	PCI_PAR : InOut std_logic;\r
	23	PCI_PERRn : Out std_logic;\r
	24	PCI_SERRn : Out std_logic;\r
	25	PERR : Out std_logic;\r
	26	SERR : Out std_logic );\r
	27	end PARITY;\r
	28	\r
	29	architecture SCHEMATIC of PARITY is\r
	30	\r
	31	SIGNAL gnd : std_logic := '0';\r
	32	SIGNAL vcc : std_logic := '1';\r
	33	\r
	34	signal PAR_OUT : std_logic_vector (10 downto 0);\r
	35	\r
	36	component PARITY_OUT\r
	37	Port ( OE_PCI_PAR : In std_logic;\r
	38	OE_PCI_PERR : In std_logic;\r
	39	PA_ER_RE : In std_logic;\r
	40	PAR_IN : In std_logic_vector (2 downto 0);\r
	41	PAR_REG : In std_logic;\r
	42	PCI_CLOCK : In std_logic;\r
	43	PCI_PAR_IN : In std_logic;\r
	44	PCI_RSTn : In std_logic;\r
	45	PERR_CHECK : In std_logic;\r
	46	SERR_CHECK : In std_logic;\r
	47	SERR_ENA : In std_logic;\r
	48	PCI_PAR : Out std_logic;\r
	49	PCI_PERRn : Out std_logic;\r
	50	PCI_SERRn : Out std_logic;\r
	51	PERR : Out std_logic;\r
	52	SERR : Out std_logic );\r
	53	end component;\r
	54	\r
	55	component PARITY_4\r
	56	Port ( PAR_IN : In std_logic_vector (3 downto 0);\r
	57	PAR_OUT : Out std_logic );\r
	58	end component;\r
	59	\r
	60	begin\r
	61	\r
	62	I12 : PARITY_OUT\r
	63	Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
	64	PA_ER_RE=>PA_ER_RE,\r
	65	PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),\r
	66	PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
	67	PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
	68	PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,\r
	69	SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,\r
	70	PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,\r
	71	SERR=>SERR );\r
	72	I9 : PARITY_4\r
	73	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),\r
	74	PAR_OUT=>PAR_OUT(8) );\r
	75	I11 : PARITY_4\r
	76	Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),\r
	77	PAR_OUT=>PAR_OUT(10) );\r
	78	I8 : PARITY_4\r
	79	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),\r
	80	PAR_OUT=>PAR_OUT(7) );\r
	81	I7 : PARITY_4\r
	82	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),\r
	83	PAR_OUT=>PAR_OUT(6) );\r
	84	I6 : PARITY_4\r
	85	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),\r
	86	PAR_OUT=>PAR_OUT(5) );\r
	87	I5 : PARITY_4\r
	88	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),\r
	89	PAR_OUT=>PAR_OUT(4) );\r
	90	I4 : PARITY_4\r
	91	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),\r
	92	PAR_OUT=>PAR_OUT(3) );\r
	93	I3 : PARITY_4\r
	94	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),\r
	95	PAR_OUT=>PAR_OUT(2) );\r
	96	I2 : PARITY_4\r
	97	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),\r
	98	PAR_OUT=>PAR_OUT(1) );\r
	99	I1 : PARITY_4\r
	100	Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),\r
	101	PAR_OUT=>PAR_OUT(0) );\r
	102	I10 : PARITY_4\r
	103	Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),\r
	104	PAR_OUT=>PAR_OUT(9) );\r
	105	\r
	106	end SCHEMATIC;\r