1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name: pci_target32_sm.v ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Tadej Markovic, tadej@opencores.org ////
10 //// ////
11 //// All additional information is avaliable in the README.txt ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_target32_sm.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.11 2003/12/19 11:11:30 mihad
49 // Compact PCI Hot Swap support added.
50 // New testcases added.
51 // Specification updated.
52 // Test application changed to support WB B3 cycles.
53 //
54 // Revision 1.10 2003/08/08 16:36:33 tadejm
55 // Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
56 //
57 // Revision 1.9 2003/01/27 16:49:31 mihad
58 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
59 //
60 // Revision 1.8 2003/01/21 16:06:56 mihad
61 // Bug fixes, testcases added.
62 //
63 // Revision 1.7 2002/09/24 19:09:17 mihad
64 // Number of state bits define was removed
65 //
66 // Revision 1.6 2002/09/24 18:30:00 mihad
67 // Changed state machine encoding to true one-hot
68 //
69 // Revision 1.5 2002/08/22 09:07:06 mihad
70 // Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
71 //
72 // Revision 1.4 2002/02/19 16:32:37 mihad
73 // Modified testbench and fixed some bugs
74 //
75 // Revision 1.3 2002/02/01 15:25:12 mihad
76 // Repaired a few bugs, updated specification, added test bench files and design document
77 //
78 // Revision 1.2 2001/10/05 08:14:30 mihad
79 // Updated all files with inclusion of timescale file for simulation purposes.
80 //
81 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
82 // New project directory structure
83 //
84 //
85 86 `include "pci_constants.v"
87 88 // synopsys translate_off
89 `include "timescale.v"
90 // synopsys translate_on
91 92 module pci_target32_sm
93 (
94 // system inputs
95 clk_in,
96 reset_in,
97 // master inputs
98 pci_frame_in,
99 pci_irdy_in,
100 pci_idsel_in,
101 pci_frame_reg_in,
102 pci_irdy_reg_in,
103 pci_idsel_reg_in,
104 // target response outputs
105 pci_trdy_out,
106 pci_stop_out,
107 pci_devsel_out,
108 pci_trdy_en_out,
109 pci_stop_en_out,
110 pci_devsel_en_out,
111 ad_load_out,
112 ad_load_on_transfer_out,
113 // address, data, bus command, byte enable in/outs
114 pci_ad_reg_in,
115 pci_ad_out,
116 pci_ad_en_out,
117 pci_cbe_reg_in,
118 pci_cbe_in,
119 bckp_trdy_en_in,
120 bckp_devsel_in,
121 bckp_trdy_in,
122 bckp_stop_in,
123 pci_trdy_reg_in,
124 pci_stop_reg_in,
125 126 // backend side of state machine with control signals to pci_io_mux ...
127 address_out,
128 addr_claim_in,
129 bc_out,
130 bc0_out,
131 data_out,
132 data_in,
133 be_out,
134 next_be_out,
135 req_out,
136 rdy_out,
137 addr_phase_out,
138 bckp_devsel_out,
139 bckp_trdy_out,
140 bckp_stop_out,
141 last_reg_out,
142 frame_reg_out,
143 fetch_pcir_fifo_out,
144 load_medium_reg_out,
145 sel_fifo_mreg_out,
146 sel_conf_fifo_out,
147 load_to_pciw_fifo_out,
148 load_to_conf_out,
149 same_read_in,
150 norm_access_to_config_in,
151 read_completed_in,
152 read_processing_in,
153 target_abort_in,
154 disconect_wo_data_in,
155 disconect_w_data_in,
156 target_abort_set_out,
157 pciw_fifo_full_in,
158 pcir_fifo_data_err_in,
159 wbw_fifo_empty_in,
160 wbu_del_read_comp_pending_in,
161 wbu_frame_en_in
162 163 ) ;
164 165 /*----------------------------------------------------------------------------------------------------------------------
166 Various parameters needed for state machine and other stuff
167 ----------------------------------------------------------------------------------------------------------------------*/
168 parameter S_IDLE = 3'b001 ;
169 parameter S_WAIT = 3'b010 ;
170 parameter S_TRANSFERE = 3'b100 ;
171 172 173 /*==================================================================================================================
174 System inputs.
175 ==================================================================================================================*/
176 // PCI side clock and reset
177 input clk_in,
178 reset_in ;
179 180 181 /*==================================================================================================================
182 PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
183 module. Enables are separate signals.
184 ==================================================================================================================*/
185 // master inputs
186 input pci_frame_in,
187 pci_irdy_in,
188 pci_idsel_in ;
189 input pci_frame_reg_in,
190 pci_irdy_reg_in,
191 pci_idsel_reg_in ;
192 193 // target response outputs
194 output pci_trdy_out,
195 pci_stop_out,
196 pci_devsel_out ;
197 output pci_trdy_en_out,
198 pci_stop_en_out,
199 pci_devsel_en_out ;
200 output ad_load_out ;
201 output ad_load_on_transfer_out ;
202 // address, data, bus command, byte enable in/outs
203 input [31:0] pci_ad_reg_in ;
204 output [31:0] pci_ad_out ;
205 output pci_ad_en_out ;
206 input [3:0] pci_cbe_reg_in ;
207 input [3:0] pci_cbe_in ;
208 input bckp_trdy_en_in ;
209 input bckp_devsel_in ;
210 input bckp_trdy_in ;
211 input bckp_stop_in ;
212 input pci_trdy_reg_in ;
213 input pci_stop_reg_in ;
214 215 216 /*==================================================================================================================
217 Other side of PCI Target state machine
218 ==================================================================================================================*/
219 // Data, byte enables, bus commands and address ports
220 output [31:0] address_out ; // current request address output - registered
221 input addr_claim_in ; // current request address claim input
222 output [3:0] bc_out ; // current request bus command output - registered
223 output bc0_out ; // current cycle RW signal output
224 input [31:0] data_in ; // for read operations - current dataphase data input
225 output [31:0] data_out ; // for write operations - current request data output - registered
226 output [3:0] be_out ; // current dataphase byte enable outputs - registered
227 output [3:0] next_be_out ; // next dataphase byte enable outputs - NOT registered
228 // Port connection control signals from PCI FSM
229 output req_out ; // Read is requested to WB master
230 output rdy_out ; // DATA / ADDRESS selection when read or write - registered
231 output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
232 output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
233 output bckp_trdy_out ; // TRDY output (which is registered) equivalent
234 output bckp_stop_out ; // STOP output (which is registered) equivalent
235 output last_reg_out ; // Indicates last data phase - registered
236 output frame_reg_out ; // FRAME output signal - registered
237 output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
238 output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
239 output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
240 output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
241 output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
242 output load_to_conf_out ; // Write enable to Configuration space registers
243 244 245 /*==================================================================================================================
246 Status
247 ==================================================================================================================*/
248 input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
249 input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
250 input read_completed_in ; // Indicates that read request is completed on WB side
251 input read_processing_in ; // Indicates that read request is processing on WB side
252 input target_abort_in ; // Indicates target abort termination
253 input disconect_wo_data_in ; // Indicates disconnect without data termination
254 input disconect_w_data_in ; // Indicates disconnect with data termination
255 input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
256 input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
257 input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
258 cvs.zerfleddert.de Git - raggedstone/blame_incremental - ethernet/source/pci/pci_target32_sm.v
projects / raggedstone / blame_incremental