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1library ieee;
2
3use ieee.std_logic_1164.all;
4use ieee.std_logic_unsigned.all;
5
6entity heartbeat is
7generic (
8 divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
9);
10
11port (
12 clk_i : in std_logic;
13 nrst_i : in std_logic;
14 led2_o : out std_logic;
15 led3_o : out std_logic;
16 led4_o : out std_logic;
17 led5_o : out std_logic;
18 led6_o : out std_logic;
19 led7_o : out std_logic;
20 led8_o : out std_logic;
21 led9_o : out std_logic
22);
23
24end heartbeat;
25
26architecture rtl of heartbeat is
27begin
28
29process(clk_i, nrst_i)
30variable counter : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
31variable state : std_logic_vector(7 downto 0) := "00000001";
32variable direction : std_logic := '0';
33begin
34
35if (rising_edge(clk_i)) then
36-- if nrst_i = '0' then
37-- counter := (others => '0');
38-- else
39 led2_o <= state(0);
40 led3_o <= state(1);
41 led4_o <= state(2);
42 led5_o <= state(3);
43 led6_o <= state(4);
44 led7_o <= state(5);
45 led8_o <= state(6);
46 led9_o <= state(7);
47 counter := counter + 1;
48 if counter = divider then
49 if state(3) = '1' then
50 direction := '1';
51 end if;
52
53 if state(0) = '1' then
54 direction := '0';
55 end if;
56
57 if direction = '0' then
58 state(7 downto 1) := state(6 downto 0);
59 state(0) := '0';
60 else
61 state(6 downto 0) := state(7 downto 1);
62 state(7) := '0';
63 end if;
64 counter := (others => '0');
65 end if;
66-- end if;
67end if;
68end process;
69end architecture;
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