cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/fifo_io_control.vhd

   1 -- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
   2
   3 library IEEE;
   4 use IEEE.std_logic_1164.all;
   5
   6 entity FIFO_IO_CONTROL is
   7         port
   8         (
   9                 PCI_CLOCK :in std_logic;
  10                 WRITE_XX1_0 :in std_logic; -- PCI Write
  11                 FIFO_RDn :in std_logic; -- FIFO Read (low active)
  12                 RESET :in std_logic;
  13                 SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
  14                 SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
  15                 S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
  16                 R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
  17                 S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
  18                 R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
  19                 S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
  20                 R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
  21                 S_ERROR :out std_logic; -- Send ERROR
  22                 R_ERROR :out std_logic; -- Recv ERROR
  23                 SR_ERROR :out std_logic -- Send / Recv Error
  24         );
  25 end entity FIFO_IO_CONTROL;
  26
  27 architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
  28
  29         signal SIG_S_ERROR :std_logic; -- Send Error
  30         signal SIG_R_ERROR :std_logic; -- Recv Error
  31
  32 begin
  33
  34  -- FIFO Write
  35
  36         process (PCI_CLOCK)
  37         begin
  38                 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
  39                         if (RESET = '1') then
  40                                 S_FIFO_WRITEn <= '1';
  41                                 SIG_S_ERROR <= '0';
  42
  43                         elsif (WRITE_XX1_0 = '0') then
  44                                 S_FIFO_WRITEn <= '1';
  45
  46                         elsif (WRITE_XX1_0 = '1') then
  47                                 if (SYNC_FLAG_7 = '0') then
  48                                         SIG_S_ERROR <= '1';
  49
  50                                 elsif (SYNC_FLAG_7 = '1') then
  51                                         S_FIFO_WRITEn <= '0';
  52                                         SIG_S_ERROR <= '0';
  53                                 end if;
  54                         end if;
  55                 end if;
  56         end process;
  57
  58         S_ERROR <= SIG_S_ERROR;
  59
  60  -- FIFO Read
  61
  62         R_FIFO_READn <= FIFO_RDn;
  63
  64 -- Receive Error
  65
  66         process (PCI_CLOCK)
  67         begin
  68                 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
  69                         if (RESET = '1') then
  70                                 SIG_R_ERROR <= '0';
  71
  72                         elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
  73                                 SIG_R_ERROR <= '1';
  74                         end if;
  75                 end if;
  76         end process;
  77
  78         R_ERROR <= SIG_R_ERROR;
  79
  80 -- Send or Receive Error
  81
  82         process (PCI_CLOCK)
  83         begin
  84                 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
  85                         SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
  86                 end if;
  87         end process;
  88
  89 -- FIFO Reset
  90
  91         process (PCI_CLOCK)
  92         begin
  93                 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
  94                         S_FIFO_RESETn <= not RESET;
  95                         R_FIFO_RESETn <= not RESET;
  96                 end if;
  97         end process;
  98
  99
 100 -- FIFO Retransmit
 101
 102         process (PCI_CLOCK)
 103         begin
 104                 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
 105                         S_FIFO_RETRANSMITn <= '1';
 106                         R_FIFO_RETRANSMITn <= '1';
 107                 end if;
 108         end process;
 109
 110 end architecture FIFO_IO_CONTROL_DESIGN;