cvs.zerfleddert.de Git - raggedstone/blob - dhwk_old/source/top_dhwk.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5
   6 entity dhwk is
   7 port (
   8
   9     -- General
  10     PCI_CLK     : in std_logic;
  11     PCI_nRES    : in std_logic;
  12
  13     -- PCI target 32bits
  14     PCI_AD      : inout std_logic_vector(31 downto 0);
  15     PCI_CBE     : in std_logic_vector(3 downto 0);
  16     PCI_PAR     : out std_logic;
  17     PCI_nFRAME  : in std_logic;
  18     PCI_nIRDY   : in std_logic;
  19     PCI_nTRDY   : out std_logic;
  20     PCI_nDEVSEL : out std_logic;
  21     PCI_nSTOP   : out std_logic;
  22     PCI_IDSEL   : in std_logic;
  23     PCI_nPERR   : out std_logic;
  24     PCI_nSERR   : out std_logic;
  25     PCI_nINT    : out std_logic;
  26
  27         -- debug signals
  28         LED3    : out std_logic;
  29         LED2    : out std_logic;
  30         LED4            : out std_logic;
  31         LED5            : out std_logic
  32
  33 );
  34 end dhwk;
  35
  36
  37 architecture dhwk_arch of dhwk is
  38
  39
  40 component pci32tlite
  41 port (
  42
  43     -- General
  44     clk33       : in std_logic;
  45     nrst            : in std_logic;
  46
  47     -- PCI target 32bits
  48     ad          : inout std_logic_vector(31 downto 0);
  49     cbe         : in std_logic_vector(3 downto 0);
  50     par         : out std_logic;
  51     frame       : in std_logic;
  52     irdy        : in std_logic;
  53     trdy        : out std_logic;
  54     devsel      : out std_logic;
  55     stop        : out std_logic;
  56     idsel       : in std_logic;
  57     perr        : out std_logic;
  58     serr        : out std_logic;
  59     intb        : out std_logic;
  60
  61         -- Master whisbone
  62     wb_adr_o     : out std_logic_vector(24 downto 1);
  63         wb_dat_i     : in std_logic_vector(15 downto 0);
  64     wb_dat_o     : out std_logic_vector(15 downto 0);
  65         wb_sel_o     : out std_logic_vector(1 downto 0);
  66     wb_we_o      : out std_logic;
  67         wb_stb_o     : out std_logic;
  68         wb_cyc_o     : out std_logic;
  69         wb_ack_i     : in std_logic;
  70         wb_err_i     : in std_logic;
  71         wb_int_i     : in std_logic;
  72
  73         -- debug signals
  74         debug_init       : out std_logic;
  75         debug_access : out std_logic
  76
  77         );
  78 end component;
  79
  80 component heartbeat
  81 port (
  82         clk_i : in std_logic;
  83         nrst_i : in std_logic;
  84         led2_o : out std_logic;
  85         led3_o : out std_logic;
  86         led4_o : out std_logic;
  87         led5_o : out std_logic
  88 );
  89 end component;
  90
  91 component generic_fifo_sc_a
  92 port (
  93         clk             : in std_logic;
  94         rst             : in std_logic;
  95         clr             : in std_logic;
  96         din             : in std_logic_vector(7 downto 0);
  97         we              : in std_logic;
  98         dout            : out std_logic_vector(7 downto 0);
  99         re              : in std_logic;
 100         full            : out std_logic;
 101         full_r          : out std_logic;
 102         empty           : out std_logic;
 103         empty_r         : out std_logic;
 104         full_n          : out std_logic;
 105         full_n_r        : out std_logic;
 106         empty_n         : out std_logic;
 107         empty_n_r       : out std_logic;
 108         level           : out std_logic_vector(1 downto 0)
 109 );
 110 end component;
 111
 112 component wb_fifo
 113 port (
 114         clk_i           : in std_logic;
 115         nrst_i          : in std_logic;
 116
 117         wb_adr_i        : in std_logic_vector(24 downto 1);
 118         wb_dat_o        : out std_logic_vector(15 downto 0);
 119         wb_dat_i        : in std_logic_vector(15 downto 0);
 120         wb_sel_i        : in std_logic_vector(1 downto 0);
 121         wb_we_i         : in std_logic;
 122         wb_stb_i        : in std_logic;
 123         wb_cyc_i        : in std_logic;
 124         wb_ack_o        : out std_logic;
 125         wb_err_o        : out std_logic;
 126         wb_int_o        : out std_logic;
 127
 128         fifo_data_i     : in std_logic_vector(7 downto 0);
 129         fifo_data_o     : out std_logic_vector(7 downto 0);
 130
 131         fifo_we_out     : out std_logic;
 132         fifo_re_out     : out std_logic
 133 );
 134 end component;
 135
 136 signal  wb_adr :                std_logic_vector(24 downto 1);
 137 signal  wb_dat_out :    std_logic_vector(15 downto 0);
 138 signal  wb_dat_in :             std_logic_vector(15 downto 0);
 139 signal  wb_sel :                std_logic_vector(1 downto 0);
 140 signal  wb_we :                 std_logic;
 141 signal  wb_stb :                std_logic;
 142 signal  wb_cyc :                std_logic;
 143 signal  wb_ack :                std_logic;
 144 signal  wb_err :                std_logic;
 145 signal  wb_int :                std_logic;
 146
 147
 148 begin
 149
 150 u_pci: component pci32tlite
 151 port map(
 152         clk33 =>                PCI_CLK,
 153         nrst =>                 PCI_nRES,
 154         ad =>                   PCI_AD,
 155         cbe =>                  PCI_CBE,
 156         par =>                  PCI_PAR,
 157         frame =>                PCI_nFRAME,
 158         irdy =>         PCI_nIRDY,
 159         trdy =>         PCI_nTRDY,
 160         devsel =>       PCI_nDEVSEL,
 161         stop =>         PCI_nSTOP,
 162         idsel =>        PCI_IDSEL,
 163         perr =>         PCI_nPERR,
 164         serr =>         PCI_nSERR,
 165         intb =>         PCI_nINT,
 166         wb_adr_o =>             wb_adr,
 167                 wb_dat_i =>             wb_dat_out,
 168         wb_dat_o =>     wb_dat_in,
 169                 wb_sel_o =>             wb_sel,
 170         wb_we_o =>              wb_we,
 171                 wb_stb_o =>             wb_stb,
 172                 wb_cyc_o =>             wb_cyc,
 173                 wb_ack_i =>             wb_ack,
 174                 wb_err_i =>             wb_err,
 175                 wb_int_i =>             wb_int
 176 --              debug_init =>   LED3,
 177 --              debug_access => LED2
 178                 );
 179
 180 my_heartbeat: component heartbeat
 181 port map(
 182         clk_i => PCI_CLK,
 183         nrst_i => PCI_nRES,
 184         led2_o => LED2,
 185         led3_o => LED3,
 186         led4_o => LED4,
 187         led5_o => LED5
 188 );
 189
 190 end dhwk_arch;