cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/vergleich.vhd

   1 -- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity VERGLEICH is
  10         Port ( IN_A : In std_logic_vector (31 downto 0);
  11                IN_B : In std_logic_vector (31 downto 0);
  12                GLEICH_OUT : Out std_logic );
  13 end VERGLEICH;
  14
  15 architecture SCHEMATIC of VERGLEICH is
  16
  17         SIGNAL gnd : std_logic := '0';
  18         SIGNAL vcc : std_logic := '1';
  19
  20         signal GLEICH : std_logic_vector (7 downto 0);
  21
  22         component VERG_2
  23                 Port ( IN_A : In std_logic_vector (1 downto 0);
  24                        IN_B : In std_logic_vector (1 downto 0);
  25                        GLEICH : Out std_logic );
  26         end component;
  27
  28         component VERG_8
  29                 Port ( GLEICH : In std_logic_vector (7 downto 0);
  30                        GLEICH_OUT : Out std_logic );
  31         end component;
  32
  33         component VERG_4
  34                 Port ( IN_A : In std_logic_vector (3 downto 0);
  35                        IN_B : In std_logic_vector (3 downto 0);
  36                        GLEICH : Out std_logic );
  37         end component;
  38
  39 begin
  40
  41         I11 : VERG_2
  42         Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
  43         IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
  44         I9 : VERG_8
  45         Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
  46                    GLEICH_OUT=>GLEICH_OUT );
  47         I8 : VERG_4
  48         Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
  49         IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
  50         I7 : VERG_4
  51         Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
  52         IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
  53         I6 : VERG_4
  54         Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
  55         IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
  56         I5 : VERG_4
  57         Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
  58         IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
  59         I4 : VERG_4
  60         Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
  61         IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
  62         I3 : VERG_4
  63         Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
  64         IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
  65         I2 : VERG_4
  66         Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
  67         IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
  68
  69 end SCHEMATIC;