cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/fifo_control.vhd

   1 -- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
   2
   3
   4
   5 LIBRARY ieee;
   6
   7 USE ieee.std_logic_1164.ALL;
   8 USE ieee.numeric_std.ALL;
   9
  10
  11 entity FIFO_CONTROL is
  12       Port ( FIFO_RDn : In    std_logic;
  13              FLAG_IN_0 : In    std_logic;
  14              FLAG_IN_4 : In    std_logic;
  15                 HOLD : In    std_logic;
  16              KONST_1 : In    std_logic;
  17              PCI_CLOCK : In    std_logic;
  18              PSC_ENABLE : In    std_logic;
  19                R_EFn : In    std_logic;
  20                R_FFn : In    std_logic;
  21                R_HFn : In    std_logic;
  22                RESET : In    std_logic;
  23                S_EFn : In    std_logic;
  24                S_FFn : In    std_logic;
  25              S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
  26                S_HFn : In    std_logic;
  27              SERIAL_IN : In    std_logic;
  28              SPC_ENABLE : In    std_logic;
  29              SPC_RDY_IN : In    std_logic;
  30              WRITE_XX1_0 : In    std_logic;
  31              R_ERROR : Out   std_logic;
  32              R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
  33              R_FIFO_READn : Out   std_logic;
  34              R_FIFO_RESETn : Out   std_logic;
  35              R_FIFO_RETRANSMITn : Out   std_logic;
  36              R_FIFO_WRITEn : Out   std_logic;
  37              RESERVE : Out   std_logic;
  38              S_ERROR : Out   std_logic;
  39              S_FIFO_READn : Out   std_logic;
  40              S_FIFO_RESETn : Out   std_logic;
  41              S_FIFO_RETRANSMITn : Out   std_logic;
  42              S_FIFO_WRITEn : Out   std_logic;
  43              SERIAL_OUT : Out   std_logic;
  44              SPC_RDY_OUT : Out   std_logic;
  45              SR_ERROR : Out   std_logic;
  46              SYNC_FLAG : Out   std_logic_vector (7 downto 0));
  47 end FIFO_CONTROL;
  48
  49 architecture SCHEMATIC of FIFO_CONTROL is
  50
  51    SIGNAL gnd : std_logic := '0';
  52    SIGNAL vcc : std_logic := '1';
  53
  54    signal XXXR_FIFO_WRITEn : std_logic;
  55    signal XXXS_FIFO_READn : std_logic;
  56    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
  57    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
  58
  59    component SER_PAR_CON
  60       Port ( PCI_CLOCK : In    std_logic;
  61                RESET : In    std_logic;
  62              SERIAL_IN : In    std_logic;
  63              SPC_ENABLE : In    std_logic;
  64              SYNC_R_FIFO_FFn : In    std_logic;
  65              PAR_OUT : Out   std_logic_vector (7 downto 0);
  66              R_FIFO_WRITEn : Out   std_logic;
  67              SPC_RDY_OUT : Out   std_logic );
  68    end component;
  69
  70    component PAR_SER_CON
  71       Port (  PAR_IN : In    std_logic_vector (7 downto 0);
  72              PCI_CLOCK : In    std_logic;
  73              PSC_ENABLE : In    std_logic;
  74                RESET : In    std_logic;
  75              SPC_RDY_IN : In    std_logic;
  76              SYNC_S_FIFO_EFn : In    std_logic;
  77              S_FIFO_READn : Out   std_logic;
  78              SER_OUT : Out   std_logic );
  79    end component;
  80
  81    component FIFO_IO_CONTROL
  82       Port ( FIFO_RDn : In    std_logic;
  83              PCI_CLOCK : In    std_logic;
  84                RESET : In    std_logic;
  85              SYNC_FLAG_1 : In    std_logic;
  86              SYNC_FLAG_7 : In    std_logic;
  87              WRITE_XX1_0 : In    std_logic;
  88              R_ERROR : Out   std_logic;
  89              R_FIFO_READn : Out   std_logic;
  90              R_FIFO_RESETn : Out   std_logic;
  91              R_FIFO_RETRANSMITn : Out   std_logic;
  92              S_ERROR : Out   std_logic;
  93              S_FIFO_RESETn : Out   std_logic;
  94              S_FIFO_RETRANSMITn : Out   std_logic;
  95              S_FIFO_WRITEn : Out   std_logic;
  96              SR_ERROR : Out   std_logic );
  97    end component;
  98
  99    component CONNECTING_FSM
 100       Port ( PCI_CLOCK : In    std_logic;
 101              PSC_ENABLE : In    std_logic;
 102                RESET : In    std_logic;
 103              S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
 104              SPC_ENABLE : In    std_logic;
 105              SYNC_R_FIFO_FFn : In    std_logic;
 106              SYNC_S_FIFO_EFn : In    std_logic;
 107              R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
 108              R_FIFO_WRITEn : Out   std_logic;
 109              S_FIFO_READn : Out   std_logic );
 110    end component;
 111
 112    component FLAG_BUS
 113       Port ( FLAG_IN_0 : In    std_logic;
 114              FLAG_IN_4 : In    std_logic;
 115                 HOLD : In    std_logic;
 116               KONS_1 : In    std_logic;
 117              PCI_CLOCK : In    std_logic;
 118                R_EFn : In    std_logic;
 119                R_FFn : In    std_logic;
 120                R_HFn : In    std_logic;
 121                S_EFn : In    std_logic;
 122                S_FFn : In    std_logic;
 123                S_HFn : In    std_logic;
 124              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
 125    end component;
 126
 127 begin
 128
 129    SYNC_FLAG <= SYNC_FLAG_DUMMY;
 130
 131    RESERVE <= gnd;
 132    I23 : SER_PAR_CON
 133       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
 134                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
 135                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
 136                  PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
 137                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
 138    I22 : PAR_SER_CON
 139       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 140                  PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
 141                  RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
 142                  SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
 143                  S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
 144    I21 : FIFO_IO_CONTROL
 145       Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
 146                  SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
 147                  SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
 148                  WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
 149                  R_FIFO_READn=>R_FIFO_READn,
 150                  R_FIFO_RESETn=>R_FIFO_RESETn,
 151                  R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
 152                  S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
 153                  S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
 154                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
 155    I20 : CONNECTING_FSM
 156       Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
 157                  RESET=>RESET,
 158                  S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 159                  SPC_ENABLE=>SPC_ENABLE,
 160                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
 161                  SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
 162                  R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
 163                  R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
 164                  S_FIFO_READn=>XXXS_FIFO_READn );
 165    I19 : FLAG_BUS
 166       Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
 167                  KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
 168                  R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
 169                  S_HFn=>S_HFn,
 170                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
 171
 172 end SCHEMATIC;