cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/top.vhd

   1 LIBRARY ieee;
   2 USE ieee.std_logic_1164.ALL;
   3
   4 entity ethernet is
   5 PORT(
   6         PCI_AD : INOUT std_logic_vector(31 downto 0);
   7         PCI_CLOCK : IN std_logic;
   8         PCI_IDSEL : IN std_logic;
   9         PCI_CBEn : INOUT std_logic_vector (3 downto 0);
  10         PCI_FRAMEn : INOUT std_logic;
  11         PCI_IRDYn : INOUT std_logic;
  12         PCI_RSTn : INOUT std_logic;
  13         PCI_DEVSELn : INOUT std_logic;
  14         PCI_INTAn : INOUT std_logic;
  15         PCI_PERRn : INOUT std_logic;
  16         PCI_SERRn : INOUT std_logic;
  17         PCI_STOPn : INOUT std_logic;
  18         PCI_TRDYn : INOUT std_logic;
  19         PCI_PAR   : INOUT std_logic;
  20         PCI_REQn  : OUT std_logic;
  21         PCI_GNTn : IN std_logic;
  22
  23         MTX_CLK_PAD_I : IN std_logic;
  24         MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
  25         MTXEN_PAD_O : OUT std_logic;
  26         MRX_CLK_PAD_I : IN std_logic;
  27         MRXD_PAD_I : IN std_logic_vector (3 downto 0);
  28         MRXDV_PAD_I : IN std_logic;
  29         MRXERR_PAD_I : IN std_logic;
  30         MCOLL_PAD_I : IN std_logic;
  31         MCRS_PAD_I : IN std_logic;
  32         MD_PAD_IO : INOUT std_logic;
  33         MDC_PAD_O : OUT std_logic;
  34
  35         PHY_CLOCK : OUT std_logic;
  36
  37         LED_2 : OUT std_logic
  38 );
  39 end ethernet;
  40
  41 architecture ethernet_arch of ethernet is
  42
  43 COMPONENT eth_top
  44 PORT(
  45         wb_clk_i : IN std_logic;
  46         wb_rst_i : IN std_logic;
  47         wb_dat_i : IN std_logic_vector(31 downto 0);
  48         wb_adr_i : IN std_logic_vector(11 downto 2);
  49         wb_sel_i : IN std_logic_vector(3 downto 0);
  50         wb_we_i : IN std_logic;
  51         wb_cyc_i : IN std_logic;
  52         wb_stb_i : IN std_logic;
  53         m_wb_dat_i : IN std_logic_vector(31 downto 0);
  54         m_wb_ack_i : IN std_logic;
  55         m_wb_err_i : IN std_logic;
  56         mtx_clk_pad_i : IN std_logic;
  57         mrx_clk_pad_i : IN std_logic;
  58         mrxd_pad_i : IN std_logic_vector(3 downto 0);
  59         mrxdv_pad_i : IN std_logic;
  60         mrxerr_pad_i : IN std_logic;
  61         mcoll_pad_i : IN std_logic;
  62         mcrs_pad_i : IN std_logic;
  63         md_pad_i : IN std_logic;
  64         wb_dat_o : OUT std_logic_vector(31 downto 0);
  65         wb_ack_o : OUT std_logic;
  66         wb_err_o : OUT std_logic;
  67         m_wb_adr_o : OUT std_logic_vector(31 downto 0);
  68         m_wb_sel_o : OUT std_logic_vector(3 downto 0);
  69         m_wb_we_o : OUT std_logic;
  70         m_wb_dat_o : OUT std_logic_vector(31 downto 0);
  71         m_wb_cyc_o : OUT std_logic;
  72         m_wb_stb_o : OUT std_logic;
  73         mtxd_pad_o : OUT std_logic_vector(3 downto 0);
  74         mtxen_pad_o : OUT std_logic;
  75         mtxerr_pad_o : OUT std_logic;
  76         mdc_pad_o : OUT std_logic;
  77         md_pad_o : OUT std_logic;
  78         md_padoe_o : OUT std_logic;
  79         m_wb_cti_o : OUT std_logic_vector(2 downto 0);
  80         m_wb_bte_o : OUT std_logic_vector(1 downto 0);
  81         int_o : OUT std_logic
  82         );
  83 END COMPONENT;
  84
  85 COMPONENT pci_bridge32
  86 PORT(
  87         wb_clk_i : IN std_logic;
  88         wb_rst_i : IN std_logic;
  89         wb_int_i : IN std_logic;
  90         wbs_adr_i : IN std_logic_vector(31 downto 0);
  91         wbs_dat_i : IN std_logic_vector(31 downto 0);
  92         wbs_sel_i : IN std_logic_vector(3 downto 0);
  93         wbs_cyc_i : IN std_logic;
  94         wbs_stb_i : IN std_logic;
  95         wbs_we_i : IN std_logic;
  96         wbs_cti_i : IN std_logic_vector(2 downto 0);
  97         wbs_bte_i : IN std_logic_vector(1 downto 0);
  98         wbm_dat_i : IN std_logic_vector(31 downto 0);
  99         wbm_ack_i : IN std_logic;
 100         wbm_rty_i : IN std_logic;
 101         wbm_err_i : IN std_logic;
 102         pci_clk_i : IN std_logic;
 103         pci_rst_i : IN std_logic;
 104         pci_inta_i : IN std_logic;
 105         pci_gnt_i : IN std_logic;
 106         pci_frame_i : IN std_logic;
 107         pci_irdy_i : IN std_logic;
 108         pci_idsel_i : IN std_logic;
 109         pci_devsel_i : IN std_logic;
 110         pci_trdy_i : IN std_logic;
 111         pci_stop_i : IN std_logic;
 112         pci_ad_i : IN std_logic_vector(31 downto 0);
 113         pci_cbe_i : IN std_logic_vector(3 downto 0);
 114         pci_par_i : IN std_logic;
 115         pci_perr_i : IN std_logic;
 116         wb_rst_o : OUT std_logic;
 117         wb_int_o : OUT std_logic;
 118         wbs_dat_o : OUT std_logic_vector(31 downto 0);
 119         wbs_ack_o : OUT std_logic;
 120         wbs_rty_o : OUT std_logic;
 121         wbs_err_o : OUT std_logic;
 122         wbm_adr_o : OUT std_logic_vector(31 downto 0);
 123         wbm_dat_o : OUT std_logic_vector(31 downto 0);
 124         wbm_sel_o : OUT std_logic_vector(3 downto 0);
 125         wbm_cyc_o : OUT std_logic;
 126         wbm_stb_o : OUT std_logic;
 127         wbm_we_o : OUT std_logic;
 128         wbm_cti_o : OUT std_logic_vector(2 downto 0);
 129         wbm_bte_o : OUT std_logic_vector(1 downto 0);
 130         pci_rst_o : OUT std_logic;
 131         pci_inta_o : OUT std_logic;
 132         pci_rst_oe_o : OUT std_logic;
 133         pci_inta_oe_o : OUT std_logic;
 134         pci_req_o : OUT std_logic;
 135         pci_req_oe_o : OUT std_logic;
 136         pci_frame_o : OUT std_logic;
 137         pci_frame_oe_o : OUT std_logic;
 138         pci_irdy_oe_o : OUT std_logic;
 139         pci_devsel_oe_o : OUT std_logic;
 140         pci_trdy_oe_o : OUT std_logic;
 141         pci_stop_oe_o : OUT std_logic;
 142         pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
 143         pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
 144         pci_irdy_o : OUT std_logic;
 145         pci_devsel_o : OUT std_logic;
 146         pci_trdy_o : OUT std_logic;
 147         pci_stop_o : OUT std_logic;
 148         pci_ad_o : OUT std_logic_vector(31 downto 0);
 149         pci_cbe_o : OUT std_logic_vector(3 downto 0);
 150         pci_par_o : OUT std_logic;
 151         pci_par_oe_o : OUT std_logic;
 152         pci_perr_o : OUT std_logic;
 153         pci_perr_oe_o : OUT std_logic;
 154         pci_serr_o : OUT std_logic;
 155         pci_serr_oe_o : OUT std_logic
 156         );
 157 END COMPONENT;
 158
 159 component icon
 160 port (
 161         control0 : out std_logic_vector(35 downto 0)
 162         );
 163 end component;
 164
 165 component ila
 166 port (
 167         control : in std_logic_vector(35 downto 0);
 168         clk : in std_logic;
 169         data : in std_logic_vector(63 downto 0);
 170         trig0 : in std_logic_vector(31 downto 0)
 171         );
 172 end component;
 173
 174 signal pci_rst_o : std_logic;
 175 signal pci_rst_oe_o : std_logic;
 176 signal pci_inta_o : std_logic;
 177 signal pci_inta_oe_o : std_logic;
 178 signal pci_req_o : std_logic;
 179 signal pci_req_oe_o : std_logic;
 180 signal pci_frame_o : std_logic;
 181 signal pci_frame_oe_o : std_logic;
 182 signal pci_irdy_o : std_logic;
 183 signal pci_irdy_oe_o : std_logic;
 184 signal pci_devsel_o : std_logic;
 185 signal pci_devsel_oe_o : std_logic;
 186 signal pci_trdy_o : std_logic;
 187 signal pci_trdy_oe_o : std_logic;
 188 signal pci_stop_o : std_logic;
 189 signal pci_stop_oe_o : std_logic;
 190 signal pci_par_o : std_logic;
 191 signal pci_par_oe_o : std_logic;
 192 signal pci_perr_o : std_logic;
 193 signal pci_perr_oe_o : std_logic;
 194 signal pci_serr_o : std_logic;
 195 signal pci_serr_oe_o : std_logic;
 196 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
 197 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
 198 signal pci_ad_o : std_logic_vector (31 downto 0);
 199 signal pci_cbe_o : std_logic_vector (3 downto 0);
 200
 201 signal wb_clk_i : std_logic;
 202 signal wb_rst_i : std_logic;
 203 signal wb_dat_i : std_logic_vector (31 downto 0);
 204 signal wb_dat_o : std_logic_vector (31 downto 0);
 205 signal wb_adr_i : std_logic_vector (11 downto 2);
 206 signal wb_sel_i : std_logic_vector (3 downto 0);
 207 signal wb_we_i : std_logic;
 208 signal wb_cyc_i : std_logic;
 209 signal wb_stb_i : std_logic;
 210 signal wb_ack_o : std_logic;
 211 signal wb_err_o : std_logic;
 212 signal m_wb_adr_o : std_logic_vector(31 downto 0);
 213 signal m_wb_sel_o : std_logic_vector(3 downto 0);
 214 signal m_wb_we_o : std_logic;
 215 signal m_wb_dat_o : std_logic_vector(31 downto 0);
 216 signal m_wb_dat_i : std_logic_vector(31 downto 0);
 217 signal m_wb_cyc_o : std_logic;
 218 signal m_wb_stb_o : std_logic;
 219 signal m_wb_ack_i : std_logic;
 220 signal m_wb_err_i : std_logic;
 221 signal md_pad_o : std_logic;
 222 signal md_padoe_o : std_logic;
 223 signal int_o : std_logic;
 224 signal wbm_adr_o : std_logic_vector(31 downto 0);
 225
 226 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 227 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 228
 229 signal control0 : std_logic_vector(35 downto 0);
 230 signal data : std_logic_vector(63 downto 0);
 231 signal trig0 : std_logic_vector(31 downto 0);
 232
 233
 234 BEGIN
 235
 236 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
 237 PCI_INTAn   <= pci_inta_o   when (pci_inta_oe_o = '1')    else 'Z';
 238 PCI_REQn    <= pci_req_o    when (pci_req_oe_o = '1')     else 'Z';
 239 PCI_FRAMEn  <= pci_frame_o  when (pci_frame_oe_o = '1')     else 'Z';
 240 PCI_IRDYn   <= pci_irdy_o   when (pci_irdy_oe_o = '1')    else 'Z';
 241 PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1')  else 'Z';
 242 PCI_TRDYn   <= pci_trdy_o   when (pci_trdy_oe_o = '1')    else 'Z';
 243 PCI_STOPn   <= pci_stop_o   when (pci_stop_oe_o = '1')    else 'Z';
 244 PCI_PAR     <= pci_par_o    when (pci_par_oe_o = '1')     else 'Z';
 245 PCI_PERRn   <= pci_perr_o   when (pci_perr_oe_o = '1')    else 'Z';
 246 PCI_SERRn   <= pci_serr_o   when (pci_serr_oe_o = '1')    else 'Z';
 247 MD_PAD_IO   <= md_pad_o     when (md_padoe_o = '1')       else 'Z';
 248
 249 BLA1: FOR i in 31 downto 0 generate
 250 PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
 251 end generate;
 252
 253 BLA2: FOR i in 3 downto 0 generate
 254 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 255 end generate;
 256
 257 wb_adr_i(11 downto 8) <= (others => '0');
 258 wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 259
 260 wb_clk_i <= PCI_CLOCK;
 261 PHY_CLOCK <= PCI_CLOCK;
 262
 263 data(31 downto 0)  <= wbm_adr_o;
 264 data(40 downto 33) <= wbm_adr_o (7 downto 0);
 265 data(63 downto 41) <= (others => '0');
 266
 267 trig0(31 downto 0) <= (
 268         0 => wb_stb_i,
 269         others => '0'
 270 );
 271
 272 Inst_pci_bridge32: pci_bridge32 PORT MAP(
 273         wb_clk_i => wb_clk_i ,
 274         wb_rst_i => '0',
 275         wb_rst_o => wb_rst_i,
 276         wb_int_i => int_o,
 277         -- wb_int_o => ,
 278         wbs_adr_i => m_wb_adr_o ,
 279         wbs_dat_i => m_wb_dat_o,
 280         wbs_dat_o => m_wb_dat_i,
 281         wbs_sel_i => m_wb_sel_o,
 282         wbs_cyc_i => m_wb_cyc_o,
 283         wbs_stb_i => m_wb_stb_o,
 284         wbs_we_i => m_wb_we_o,
 285         wbs_cti_i => m_wb_cti_o,
 286         wbs_bte_i => m_wb_bte_o,
 287         wbs_ack_o => m_wb_ack_i,
 288         -- wbs_rty_o => ,
 289         wbs_err_o => m_wb_err_i,
 290         wbm_adr_o => wbm_adr_o,
 291         wbm_dat_i => wb_dat_o,
 292         wbm_dat_o => wb_dat_i,
 293         wbm_sel_o => wb_sel_i,
 294         wbm_cyc_o => wb_cyc_i,
 295         wbm_stb_o => wb_stb_i,
 296         wbm_we_o => wb_we_i,
 297         -- wbm_cti_o => ,
 298         -- wbm_bte_o => ,
 299         wbm_ack_i => wb_ack_o ,
 300         wbm_rty_i => '0',
 301         wbm_err_i => wb_err_o,
 302         pci_clk_i => PCI_CLOCK,
 303         pci_rst_i => PCI_RSTn,
 304         pci_rst_o => pci_rst_o ,
 305         pci_rst_oe_o => pci_rst_oe_o,
 306         pci_inta_i => PCI_INTAn,
 307         pci_inta_o => pci_inta_o,
 308         pci_inta_oe_o => pci_inta_oe_o,
 309         pci_req_o => pci_req_o,
 310         pci_req_oe_o => pci_req_oe_o,
 311         pci_gnt_i => PCI_GNTn,
 312         pci_frame_i => PCI_FRAMEn,
 313         pci_frame_o => pci_frame_o,
 314         pci_frame_oe_o => pci_frame_oe_o,
 315         pci_irdy_oe_o => pci_irdy_oe_o,
 316         pci_devsel_oe_o => pci_devsel_oe_o,
 317         pci_trdy_oe_o => pci_trdy_oe_o,
 318         pci_stop_oe_o => pci_stop_oe_o,
 319         pci_ad_oe_o => pci_ad_oe_o,
 320         pci_cbe_oe_o => pci_cbe_oe_o,
 321         pci_irdy_i => PCI_IRDYn,
 322         pci_irdy_o => pci_irdy_o,
 323         pci_idsel_i => PCI_IDSEL,
 324         pci_devsel_i => PCI_DEVSELn,
 325         pci_devsel_o => pci_devsel_o,
 326         pci_trdy_i => PCI_TRDYn,
 327         pci_trdy_o => pci_trdy_o,
 328         pci_stop_i => PCI_STOPn,
 329         pci_stop_o => pci_stop_o,
 330         pci_ad_i => PCI_AD,
 331         pci_ad_o => pci_ad_o,
 332         pci_cbe_i => PCI_CBEn,
 333         pci_cbe_o => pci_cbe_o,
 334         pci_par_i => PCI_PAR,
 335         pci_par_o => pci_par_o,
 336         pci_par_oe_o => pci_par_oe_o,
 337         pci_perr_i => PCI_PERRn,
 338         pci_perr_o => pci_perr_o,
 339         pci_perr_oe_o => pci_perr_oe_o,
 340         pci_serr_o => pci_serr_o,
 341         pci_serr_oe_o =>  pci_serr_oe_o
 342 );
 343
 344 Inst_eth_top: eth_top PORT MAP(
 345         wb_clk_i   => wb_clk_i  ,
 346         wb_rst_i   => wb_rst_i  ,
 347         wb_dat_i   => wb_dat_i  ,
 348         wb_dat_o   => wb_dat_o  ,
 349         wb_adr_i   => wb_adr_i  ,
 350         wb_sel_i   => wb_sel_i  ,
 351         wb_we_i    => wb_we_i   ,
 352         wb_cyc_i   => wb_cyc_i  ,
 353         wb_stb_i   => wb_stb_i,
 354         wb_ack_o   => wb_ack_o  ,
 355         wb_err_o   => wb_err_o  ,
 356         m_wb_adr_o => m_wb_adr_o,
 357         m_wb_sel_o => m_wb_sel_o,
 358         m_wb_we_o  => m_wb_we_o ,
 359         m_wb_dat_o => m_wb_dat_o,
 360         m_wb_dat_i => m_wb_dat_i,
 361         m_wb_cyc_o => m_wb_cyc_o,
 362         m_wb_stb_o => m_wb_stb_o,
 363         m_wb_ack_i => m_wb_ack_i,
 364         m_wb_err_i => m_wb_err_i,
 365         mtx_clk_pad_i => MTX_CLK_PAD_I,
 366         mtxd_pad_o => MTXD_PAD_O,
 367         mtxen_pad_o => MTXEN_PAD_O,
 368         mtxerr_pad_o => LED_2,
 369         mrx_clk_pad_i => MRX_CLK_PAD_I,
 370         mrxd_pad_i => MRXD_PAD_I,
 371         mrxdv_pad_i => MRXDV_PAD_I,
 372         mrxerr_pad_i => MRXERR_PAD_I,
 373         mcoll_pad_i => MCOLL_PAD_I,
 374         mcrs_pad_i => MCRS_PAD_I,
 375         mdc_pad_o => MDC_PAD_O,
 376         md_pad_i => MD_PAD_IO,
 377         md_pad_o => md_pad_o,
 378         md_padoe_o => md_padoe_o,
 379         m_wb_cti_o => m_wb_cti_o,
 380         m_wb_bte_o => m_wb_bte_o,
 381         int_o => int_o
 382 );
 383
 384 i_icon : icon
 385 port map (
 386         control0 => control0
 387         );
 388
 389 i_ila : ila
 390 port map (
 391         control => control0,
 392         clk => PCI_CLOCK,
 393         data => data,
 394         trig0 => trig0
 395         );
 396
 397 end architecture ethernet_arch;