cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/top_raggedstone.vhd

   1 --+-------------------------------------------------------------------------------------------------+
   2 --|                                                                                                                                                                                                     |
   3 --|  File:                      top.vhd                                                                         |
   4 --|                                                                                                                                                                                                     |
   5 --|  Components:        pci32lite.vhd                                                                   |
   6 --|                         pciwbsequ.vhd                                                                                                                       |
   7 --|                         pcidmux.vhd                                                                                                                                 |
   8 --|                         pciregs.vhd                                                                                                                                 |
   9 --|                         pcipargen.vhd                                                                                                                               |
  10 --|                         -- Libs --                                                                                                                                  |
  11 --|                         ona.vhd                                                                                                                                             |
  12 --|                                                                                                                                                                                                     |
  13 --|      Description:   RS1 PCI Demo : (TOP) Main file.                                                                                 |
  14 --|                                                                                                                                                                                             |
  15 --|                                                                                                                                                                             |
  16 --|                                                                                                                                                                                                     |
  17 --+-------------------------------------------------------------------------------------------------+
  18 --|                                                                                                                                                                                                     |
  19 --|  Revision history :                                                                                                                                                         |
  20 --|  Date                 Version       Author  Description                                                                                                             |
  21 --|                                                                                                                                                                                                     |
  22 --|                                                                                                                                                                                                     |
  23 --|  To do:                                                                                                                                                                                     |
  24 --|                                                                                                                                                                                                     |
  25 --+-------------------------------------------------------------------------------------------------+
  26
  27
  28 --+-----------------------------------------------------------------------------+
  29 --|                                                                     LIBRARIES                                                                       |
  30 --+-----------------------------------------------------------------------------+
  31
  32 library ieee;
  33 use ieee.std_logic_1164.all;
  34 use ieee.std_logic_arith.all;
  35 use ieee.std_logic_unsigned.all;
  36
  37 --+-----------------------------------------------------------------------------+
  38 --|                                                                     ENTITY                                                                          |
  39 --+-----------------------------------------------------------------------------+
  40
  41 entity pci_7seg is
  42 port (
  43
  44     -- General
  45     PCI_CLK     : in std_logic;
  46     PCI_nRES    : in std_logic;
  47
  48     -- PCI target 32bits
  49     PCI_AD      : inout std_logic_vector(31 downto 0);
  50     PCI_CBE     : in std_logic_vector(3 downto 0);
  51     PCI_PAR     : out std_logic;
  52     PCI_nFRAME  : in std_logic;
  53     PCI_nIRDY   : in std_logic;
  54     PCI_nTRDY   : out std_logic;
  55     PCI_nDEVSEL : out std_logic;
  56     PCI_nSTOP   : out std_logic;
  57     PCI_IDSEL   : in std_logic;
  58     PCI_nPERR   : out std_logic;
  59     PCI_nSERR   : out std_logic;
  60     PCI_nINT    : out std_logic;
  61
  62         -- 7seg
  63     DISP_SEL                : inout std_logic_vector(3 downto 0);
  64     DISP_LED                : out std_logic_vector(6 downto 0);
  65
  66         -- debug signals
  67         LED_INIT         : out std_logic;
  68         LED_ACCESS       : out std_logic;
  69         LED_ALIVE : out std_logic;
  70
  71         -- vga signals
  72         hs             : out std_logic;
  73         vs             : out std_logic;
  74         red, grn, blu  : out std_logic;
  75         mclk           : in std_logic
  76
  77 );
  78 end pci_7seg;
  79
  80
  81 --+-----------------------------------------------------------------------------+
  82 --|                                                                     ARCHITECTURE                                                            |
  83 --+-----------------------------------------------------------------------------+
  84
  85 architecture pci_7seg_arch of pci_7seg is
  86
  87
  88 --+-----------------------------------------------------------------------------+
  89 --|                                                                     COMPONENTS                                                                      |
  90 --+-----------------------------------------------------------------------------+
  91
  92 component pci32tlite
  93 port (
  94
  95     -- General
  96     clk33       : in std_logic;
  97     nrst            : in std_logic;
  98
  99     -- PCI target 32bits
 100     ad          : inout std_logic_vector(31 downto 0);
 101     cbe         : in std_logic_vector(3 downto 0);
 102     par         : out std_logic;
 103     frame       : in std_logic;
 104     irdy        : in std_logic;
 105     trdy        : out std_logic;
 106     devsel      : out std_logic;
 107     stop        : out std_logic;
 108     idsel       : in std_logic;
 109     perr        : out std_logic;
 110     serr        : out std_logic;
 111     intb        : out std_logic;
 112
 113         -- Master whisbone
 114     wb_adr_o     : out std_logic_vector(24 downto 1);
 115         wb_dat_i     : in std_logic_vector(15 downto 0);
 116     wb_dat_o     : out std_logic_vector(15 downto 0);
 117         wb_sel_o     : out std_logic_vector(1 downto 0);
 118     wb_we_o      : out std_logic;
 119         wb_stb_o     : out std_logic;
 120         wb_cyc_o     : out std_logic;
 121         wb_ack_i     : in std_logic;
 122         wb_err_i     : in std_logic;
 123         wb_int_i     : in std_logic;
 124
 125         -- debug signals
 126         debug_init       : out std_logic;
 127         debug_access : out std_logic
 128
 129         );
 130 end component;
 131
 132
 133 component wb_7seg_new
 134 port (
 135
 136    -- General
 137     clk_i      : in std_logic;
 138     nrst_i         : in std_logic;
 139
 140         -- Master whisbone
 141     wb_adr_i   : in std_logic_vector(24 downto 1);
 142         wb_dat_o   : out std_logic_vector(15 downto 0);
 143     wb_dat_i   : in std_logic_vector(15 downto 0);
 144         wb_sel_i   : in std_logic_vector(1 downto 0);
 145     wb_we_i    : in std_logic;
 146         wb_stb_i   : in std_logic;
 147         wb_cyc_i   : in std_logic;
 148         wb_ack_o   : out std_logic;
 149         wb_err_o   : out std_logic;
 150         wb_int_o   : out std_logic;
 151
 152         -- 7seg
 153     DISP_SEL   : inout std_logic_vector(3 downto 0);
 154     DISP_LED   : out std_logic_vector(6 downto 0)
 155
 156    );
 157 end component;
 158
 159
 160 component vgaController is
 161         Port ( mclk : in std_logic;
 162            hs : out std_logic;
 163            vs : out std_logic;
 164            red : out std_logic;
 165            grn : out std_logic;
 166            blu : out std_logic);
 167 end component;
 168
 169
 170 --+-----------------------------------------------------------------------------+
 171 --|                                                                     CONSTANTS                                                                       |
 172 --+-----------------------------------------------------------------------------+
 173 --+-----------------------------------------------------------------------------+
 174 --|                                                                     SIGNALS                                                                         |
 175 --+-----------------------------------------------------------------------------+
 176
 177         signal  wb_adr :                std_logic_vector(24 downto 1);
 178         signal  wb_dat_out :    std_logic_vector(15 downto 0);
 179         signal  wb_dat_in :             std_logic_vector(15 downto 0);
 180         signal  wb_sel :                std_logic_vector(1 downto 0);
 181         signal  wb_we :                 std_logic;
 182         signal  wb_stb :                std_logic;
 183         signal  wb_cyc :                std_logic;
 184         signal  wb_ack :                std_logic;
 185         signal  wb_err :                std_logic;
 186         signal  wb_int :                std_logic;
 187
 188
 189 begin
 190
 191                          LED_ALIVE <= '1';
 192 --+-------------------------------------------------------------------------+
 193 --|  Component instances                                                                                                        |
 194 --+-------------------------------------------------------------------------+
 195
 196         vga1: vgaController port map (mclk => mclk,
 197                 hs => hs,
 198                 vs => vs,
 199                 red => red,
 200                 grn => grn,
 201                 blu => blu);
 202
 203 --+-----------------------------------------+
 204 --|  PCI Target                                                         |
 205 --+-----------------------------------------+
 206
 207 u_pci: component pci32tlite
 208 port map(
 209         clk33 =>                PCI_CLK,
 210         nrst =>                 PCI_nRES,
 211         ad =>                   PCI_AD,
 212         cbe =>                  PCI_CBE,
 213         par =>                  PCI_PAR,
 214         frame =>                PCI_nFRAME,
 215         irdy =>         PCI_nIRDY,
 216         trdy =>         PCI_nTRDY,
 217         devsel =>       PCI_nDEVSEL,
 218         stop =>         PCI_nSTOP,
 219         idsel =>        PCI_IDSEL,
 220         perr =>         PCI_nPERR,
 221         serr =>         PCI_nSERR,
 222         intb =>         PCI_nINT,
 223         wb_adr_o =>             wb_adr,
 224                 wb_dat_i =>             wb_dat_out,
 225         wb_dat_o =>     wb_dat_in,
 226                 wb_sel_o =>             wb_sel,
 227         wb_we_o =>              wb_we,
 228                 wb_stb_o =>             wb_stb,
 229                 wb_cyc_o =>             wb_cyc,
 230                 wb_ack_i =>             wb_ack,
 231                 wb_err_i =>             wb_err,
 232                 wb_int_i =>             wb_int,
 233                 debug_init =>   LED_INIT,
 234                 debug_access => LED_ACCESS
 235                 );
 236
 237 --+-----------------------------------------+
 238 --|  WB-7seg                                                    |
 239 --+-----------------------------------------+
 240
 241 u_wb: component wb_7seg_new
 242 port map(
 243                 clk_i    =>             PCI_CLK,
 244         nrst_i   =>             PCI_nRES,
 245         wb_adr_i =>             wb_adr,
 246                 wb_dat_o =>             wb_dat_out,
 247         wb_dat_i =>             wb_dat_in,
 248                 wb_sel_i =>             wb_sel,
 249         wb_we_i  =>     wb_we,
 250                 wb_stb_i =>             wb_stb,
 251                 wb_cyc_i =>             wb_cyc,
 252                 wb_ack_o =>             wb_ack,
 253                 wb_err_o =>             wb_err,
 254                 wb_int_o =>             wb_int,
 255                 DISP_SEL =>             DISP_SEL,
 256                 DISP_LED =>             DISP_LED
 257 );
 258
 259 end pci_7seg_arch;