cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/config_mux_0.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONFIG_MUX_0.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity CONFIG_MUX_0 is
  10         port
  11         (
  12         READ_SEL                        :in             std_logic_vector( 2 downto 0);
  13         CONF_DATA_00H   :in             std_logic_vector(31 downto 0);
  14         CONF_DATA_04H   :in             std_logic_vector(31 downto 0);
  15         CONF_DATA_08H   :in             std_logic_vector(31 downto 0);
  16         CONF_DATA_10H   :in             std_logic_vector(31 downto 0);
  17         CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);
  18 --CONF_DATA_40H :in             std_logic_vector(31 downto 0);
  19         CONF_DATA                       :out    std_logic_vector(31 downto 0)
  20     );
  21 end entity CONFIG_MUX_0;
  22
  23 architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is
  24
  25         signal  MUX     :std_logic_vector (31 downto  0);
  26
  27 begin
  28
  29 --*******************************************************************
  30 --******************* PCI Read  Config-MUX **************************
  31 --*******************************************************************
  32
  33         MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else
  34                                         CONF_DATA_04H   when READ_SEL <= "001" else
  35                                         CONF_DATA_08H   when READ_SEL <= "010" else
  36                                         CONF_DATA_10H   when READ_SEL <= "011" else
  37                                         CONF_DATA_3CH   when READ_SEL <= "100" else
  38 --                              CONF_DATA_40H   when READ_SEL <= "101" else
  39                                         X"00000000"     ;
  40
  41         CONF_DATA <= MUX ;
  42
  43
  44 end architecture CONFIG_MUX_0_DESIGN;