1 -- $Id: PAR_SER_CON.vhd,v 1.4 2007-03-11 08:44:31 sithglan Exp $
4 use ieee.std_logic_1164.all;
5 use ieee.std_logic_unsigned.all;
10 PCI_CLOCK :in std_logic;
12 PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable
13 SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active)
14 SPC_RDY_IN :in std_logic; -- Ready to receive data
15 PAR_IN :in std_logic_vector(7 downto 0);
16 SER_OUT :out std_logic; -- Serial Output
17 S_FIFO_READn :out std_logic -- FIFO Read (low active)
19 end entity PAR_SER_CON ;
21 architecture PAR_SER_CON_DESIGN of PAR_SER_CON is
23 constant STATE_END :std_logic_vector(3 downto 0) := "0001";
24 constant STATE_SEND :std_logic_vector(3 downto 0) := "0010";
25 constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
26 constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
27 constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
28 constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
29 constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
30 constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
31 constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
32 constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
34 signal COUNT :std_logic_vector (3 downto 0);
35 signal STATE :std_logic_vector (3 downto 0);
36 signal DATUM :std_logic_vector (7 downto 0);
37 signal SYNC :std_logic; -- make SPC_RDY_IN stable
39 attribute syn_state_machine:boolean;
40 attribute syn_state_machine of STATE: signal is false;
41 attribute syn_state_machine of COUNT: signal is false;
46 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
47 if ("0000" < COUNT) then
57 elsif (PSC_ENABLE = '1') then
58 if (COUNT = "0000") then
62 if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
65 STATE <= STATE_SEND_BIT_0;
68 when STATE_SEND_BIT_0 =>
72 STATE <= STATE_SEND_BIT_1;
74 when STATE_SEND_BIT_1 =>
76 STATE <= STATE_SEND_BIT_2;
78 when STATE_SEND_BIT_2 =>
80 STATE <= STATE_SEND_BIT_3;
82 when STATE_SEND_BIT_3 =>
84 STATE <= STATE_SEND_BIT_4;
86 when STATE_SEND_BIT_4 =>
88 STATE <= STATE_SEND_BIT_5;
90 when STATE_SEND_BIT_5 =>
92 STATE <= STATE_SEND_BIT_6;
94 when STATE_SEND_BIT_6 =>
96 STATE <= STATE_SEND_BIT_7;
98 when STATE_SEND_BIT_7 =>
106 when others => STATE <= STATE_END;
112 end if; -- RESET ... / PSC_ENABLE ...
113 end if; -- PCI_CLOCK ...
118 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
123 end architecture PAR_SER_CON_DESIGN;