cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/reg_io.vhd

   1 -- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity REG_IO is
  10         Port (  AD_REG : In    std_logic_vector (31 downto 0);
  11                 PCI_CLOCK : In    std_logic;
  12                 RESET : In    std_logic;
  13                 WRITE_XX1_0 : In    std_logic;
  14                 WRITE_XX7_6 : In    std_logic;
  15                 REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
  16                 REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
  17                 REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );
  18 end REG_IO;
  19
  20 architecture SCHEMATIC of REG_IO is
  21
  22         SIGNAL gnd : std_logic := '0';
  23         SIGNAL vcc : std_logic := '1';
  24
  25
  26         component REG
  27                 Port (   CLOCK : In    std_logic;
  28                          REG_IN : In    std_logic_vector (7 downto 0);
  29                          RESET : In    std_logic;
  30                          WRITE : In    std_logic;
  31                          REG_OUT : Out   std_logic_vector (7 downto 0) );
  32         end component;
  33
  34 begin
  35
  36         I14 : REG
  37         Port Map ( CLOCK=>PCI_CLOCK,
  38         REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
  39         WRITE=>WRITE_XX1_0,
  40         REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
  41         I15 : REG
  42         Port Map ( CLOCK=>PCI_CLOCK,
  43         REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
  44         WRITE=>WRITE_XX7_6,
  45         REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
  46         I16 : REG
  47         Port Map ( CLOCK=>PCI_CLOCK,
  48         REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
  49         WRITE=>WRITE_XX7_6,
  50         REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );
  51
  52 end SCHEMATIC;