cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/DATA_MUX.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: DATA_MUX.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all;
   8
   9 entity DATA_MUX is
  10         port
  11         (
  12                 READ_SEL :in std_logic_vector( 1 downto 0);
  13                 ADDR_REG :in std_logic_vector(31 downto 0);
  14                 CBE_REGn :in std_logic_vector( 3 downto 0);
  15                 MUX_IN_XX0 :in std_logic_vector( 7 downto 0);
  16                 MUX_IN_XX1 :in std_logic_vector( 7 downto 0);
  17                 MUX_IN_XX2 :in std_logic_vector( 7 downto 0);
  18                 MUX_IN_XX3 :in std_logic_vector( 7 downto 0);
  19                 MUX_IN_XX4 :in std_logic_vector( 7 downto 0);
  20                 MUX_IN_XX5 :in std_logic_vector( 7 downto 0);
  21                 MUX_IN_XX6 :in std_logic_vector( 7 downto 0);
  22                 MUX_IN_XX7 :in std_logic_vector( 7 downto 0);
  23                 MUX_OUT :out std_logic_vector(31 downto 0);
  24                 READ_XX1_0 :out std_logic;
  25                 READ_XX3_2 :out std_logic;
  26                 READ_XX5_4 :out std_logic;
  27                 READ_XX7_6 :out std_logic
  28                 --READ_FIFO :out std_logic
  29         );
  30 end entity DATA_MUX;
  31
  32 architecture DATA_MUX_DESIGN of DATA_MUX is
  33
  34         signal MUX :std_logic_vector(31 downto 0);
  35         signal SEL :std_logic_vector( 7 downto 0);
  36
  37         signal SIG_READ_XX1_0 :std_logic;
  38         signal SIG_READ_XX3_2 :std_logic;
  39         signal SIG_READ_XX5_4 :std_logic;
  40         signal SIG_READ_XX7_6 :std_logic;
  41
  42 begin
  43
  44         SEL <= ADDR_REG(3 downto 2) & CBE_REGn & READ_SEL;
  45
  46         SIG_READ_XX1_0 <= '1' when SEL = "00110011" else '0';
  47         SIG_READ_XX3_2 <= '1' when SEL = "00001111" else '0';
  48         SIG_READ_XX5_4 <= '1' when SEL = "01110011" else '0';
  49         SIG_READ_XX7_6 <= '1' when SEL = "01001111" else '0';
  50
  51         MUX <= (X"00" & X"00" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
  52                (MUX_IN_XX3 & MUX_IN_XX2 & X"00" & X"00" ) when SIG_READ_XX3_2 = '1' else
  53                (X"00" & X"00" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
  54                (MUX_IN_XX7 & MUX_IN_XX6 & X"00" & X"00" ) when SIG_READ_XX7_6 = '1' else
  55                (others => '0');
  56
  57
  58  -- MUX <= (X"01" & X"23" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
  59  -- (MUX_IN_XX3 & MUX_IN_XX2 & X"45" & X"67" ) when SIG_READ_XX3_2 = '1' else
  60  -- (X"89" & X"AB" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
  61  -- (MUX_IN_XX7 & MUX_IN_XX6 & X"CD" & X"EF" ) when SIG_READ_XX7_6 = '1' else
  62  -- (others => '0');
  63
  64
  65         MUX_OUT <= MUX;
  66
  67
  68         READ_XX1_0 <= SIG_READ_XX1_0;
  69         READ_XX3_2 <= SIG_READ_XX3_2;
  70         READ_XX5_4 <= SIG_READ_XX5_4;
  71         READ_XX7_6 <= SIG_READ_XX7_6;
  72
  73 --READ_FIFO <= SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test
  74
  75 end architecture DATA_MUX_DESIGN;