cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/top.vhd

   1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity dhwk is
  10         Port ( KONST_1 : In std_logic;
  11                PCI_CBEn : In std_logic_vector (3 downto 0);
  12                PCI_CLOCK : In std_logic;
  13                PCI_FRAMEn : In std_logic;
  14                PCI_IDSEL : In std_logic;
  15                PCI_IRDYn : In std_logic;
  16                PCI_RSTn : In std_logic;
  17                -- SERIAL_IN : In std_logic;
  18                -- SPC_RDY_IN : In std_logic;
  19                TAST_RESn : In std_logic;
  20                TAST_SETn : In std_logic;
  21                LED_2 : out std_logic;
  22                LED_3 : out std_logic;
  23                LED_4 : out std_logic;
  24                LED_5 : out std_logic;
  25                PCI_AD : InOut std_logic_vector (31 downto 0);
  26                PCI_PAR : InOut std_logic;
  27                PCI_DEVSELn : Out std_logic;
  28                PCI_INTAn : Out std_logic;
  29                PCI_PERRn : Out std_logic;
  30                PCI_SERRn : Out std_logic;
  31                PCI_STOPn : Out std_logic;
  32                PCI_TRDYn : Out std_logic;
  33                PCI_REQn : Out std_logic;
  34                PCI_GNTn : In std_logic;
  35                -- SERIAL_OUT : Out std_logic;
  36                -- SPC_RDY_OUT : Out std_logic;
  37                TB_IDSEL : Out std_logic;
  38                TB_nDEVSEL : Out std_logic;
  39                TB_nINTA : Out std_logic );
  40 end dhwk;
  41
  42 architecture SCHEMATIC of dhwk is
  43
  44         SIGNAL gnd : std_logic := '0';
  45         SIGNAL vcc : std_logic := '1';
  46
  47         signal READ_XX7_6 : std_logic;
  48         signal RESERVE : std_logic;
  49         signal SR_ERROR : std_logic;
  50         signal R_ERROR : std_logic;
  51         signal S_ERROR : std_logic;
  52         signal WRITE_XX3_2 : std_logic;
  53         signal WRITE_XX5_4 : std_logic;
  54         signal WRITE_XX7_6 : std_logic;
  55         signal READ_XX1_0 : std_logic;
  56         signal READ_XX3_2 : std_logic;
  57         signal INTAn : std_logic;
  58         signal TRDYn : std_logic;
  59         signal READ_XX5_4 : std_logic;
  60         signal DEVSELn : std_logic;
  61         signal FIFO_RDn : std_logic;
  62         signal WRITE_XX1_0 : std_logic;
  63         signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
  64         signal SYNC_FLAG : std_logic_vector (7 downto 0);
  65         signal INT_REG : std_logic_vector (7 downto 0);
  66         signal REVISON_ID : std_logic_vector (7 downto 0);
  67         signal VENDOR_ID : std_logic_vector (15 downto 0);
  68         signal READ_SEL : std_logic_vector (1 downto 0);
  69         signal AD_REG : std_logic_vector (31 downto 0);
  70         signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
  71         signal R_EFn : std_logic;
  72         signal R_FFn : std_logic;
  73         signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
  74         signal R_HFn : std_logic;
  75         signal S_EFn : std_logic;
  76         signal S_FFn : std_logic;
  77         signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
  78         signal S_HFn : std_logic;
  79         signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
  80         signal R_FIFO_READn : std_logic;
  81         signal R_FIFO_RESETn : std_logic;
  82         signal R_FIFO_RTn : std_logic;
  83         signal R_FIFO_WRITEn : std_logic;
  84         signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
  85         signal S_FIFO_READn : std_logic;
  86         signal S_FIFO_RESETn : std_logic;
  87         signal S_FIFO_RTn : std_logic;
  88         signal S_FIFO_WRITEn : std_logic;
  89         signal SERIAL_IN : std_logic;
  90         signal SPC_RDY_IN : std_logic;
  91         signal SERIAL_OUT : std_logic;
  92         signal SPC_RDY_OUT : std_logic;
  93         signal watch_PCI_INTAn : std_logic;
  94         signal watch_PCI_TRDYn : std_logic;
  95         signal watch_PCI_STOPn : std_logic;
  96         signal watch_PCI_SERRn : std_logic;
  97         signal watch_PCI_PERRn : std_logic;
  98         signal watch_PCI_REQn : std_logic;
  99         signal control0 : std_logic_vector(35 downto 0);
 100         signal data : std_logic_vector(95 downto 0);
 101         signal trig0 : std_logic_vector(31 downto 0);
 102
 103         component MESS_1_TB
 104                 Port ( DEVSELn : In std_logic;
 105                        INTAn : In std_logic;
 106                        KONST_1 : In std_logic;
 107                        PCI_IDSEL : In std_logic;
 108                        REG_OUT_XX7 : In std_logic_vector (7 downto 0);
 109                        TB_DEVSELn : Out std_logic;
 110                        TB_INTAn : Out std_logic;
 111                        TB_PCI_IDSEL : Out std_logic );
 112         end component;
 113
 114         component VEN_REV_ID
 115                 Port ( REV_ID : Out std_logic_vector (7 downto 0);
 116                        VEN_ID : Out std_logic_vector (15 downto 0) );
 117         end component;
 118
 119         component INTERRUPT
 120                 Port ( INT_IN_0 : In std_logic;
 121                        INT_IN_1 : In std_logic;
 122                        INT_IN_2 : In std_logic;
 123                        INT_IN_3 : In std_logic;
 124                        INT_IN_4 : In std_logic;
 125                        INT_IN_5 : In std_logic;
 126                        INT_IN_6 : In std_logic;
 127                        INT_IN_7 : In std_logic;
 128                        INT_MASKE : In std_logic_vector (7 downto 0);
 129                        INT_RES : In std_logic_vector (7 downto 0);
 130                        PCI_CLOCK : In std_logic;
 131                        PCI_RSTn : In std_logic;
 132                        READ_XX5_4 : In std_logic;
 133                        RESET : In std_logic;
 134                        TAST_RESn : In std_logic;
 135                        TAST_SETn : In std_logic;
 136                        TRDYn : In std_logic;
 137                        INT_REG : Out std_logic_vector (7 downto 0);
 138                        INTAn : Out std_logic;
 139                        PCI_INTAn : Out std_logic );
 140         end component;
 141
 142         component FIFO_CONTROL
 143                 Port ( FIFO_RDn : In std_logic;
 144                        FLAG_IN_0 : In std_logic;
 145                        FLAG_IN_4 : In std_logic;
 146                        HOLD : In std_logic;
 147                        KONST_1 : In std_logic;
 148                        PCI_CLOCK : In std_logic;
 149                        PSC_ENABLE : In std_logic;
 150                        R_EFn : In std_logic;
 151                        R_FFn : In std_logic;
 152                        R_HFn : In std_logic;
 153                        RESET : In std_logic;
 154                        S_EFn : In std_logic;
 155                        S_FFn : In std_logic;
 156                        S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
 157                        S_HFn : In std_logic;
 158                        SERIAL_IN : In std_logic;
 159                        SPC_ENABLE : In std_logic;
 160                        SPC_RDY_IN : In std_logic;
 161                        WRITE_XX1_0 : In std_logic;
 162                        R_ERROR : Out std_logic;
 163                        R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
 164                        R_FIFO_READn : Out std_logic;
 165                        R_FIFO_RESETn : Out std_logic;
 166                        R_FIFO_RETRANSMITn : Out std_logic;
 167                        R_FIFO_WRITEn : Out std_logic;
 168                        RESERVE : Out std_logic;
 169                        S_ERROR : Out std_logic;
 170                        S_FIFO_READn : Out std_logic;
 171                        S_FIFO_RESETn : Out std_logic;
 172                        S_FIFO_RETRANSMITn : Out std_logic;
 173                        S_FIFO_WRITEn : Out std_logic;
 174                        SERIAL_OUT : Out std_logic;
 175                        SPC_RDY_OUT : Out std_logic;
 176                        SR_ERROR : Out std_logic;
 177                        SYNC_FLAG : Out std_logic_vector (7 downto 0) );
 178         end component;
 179
 180         component PCI_TOP
 181                 Port ( FLAG : In std_logic_vector (7 downto 0);
 182                        INT_REG : In std_logic_vector (7 downto 0);
 183                        PCI_CBEn : In std_logic_vector (3 downto 0);
 184                        PCI_CLOCK : In std_logic;
 185                        PCI_FRAMEn : In std_logic;
 186                        PCI_IDSEL : In std_logic;
 187                        PCI_IRDYn : In std_logic;
 188                        PCI_RSTn : In std_logic;
 189                        R_FIFO_Q : In std_logic_vector (7 downto 0);
 190                        REVISON_ID : In std_logic_vector (7 downto 0);
 191                        VENDOR_ID : In std_logic_vector (15 downto 0);
 192                        PCI_AD : InOut std_logic_vector (31 downto 0);
 193                        PCI_PAR : InOut std_logic;
 194                        AD_REG : Out std_logic_vector (31 downto 0);
 195                        DEVSELn : Out std_logic;
 196                        FIFO_RDn : Out std_logic;
 197                        PCI_DEVSELn : Out std_logic;
 198                        PCI_PERRn : Out std_logic;
 199                        PCI_SERRn : Out std_logic;
 200                        PCI_STOPn : Out std_logic;
 201                        PCI_TRDYn : Out std_logic;
 202                        READ_SEL : Out std_logic_vector (1 downto 0);
 203                        READ_XX1_0 : Out std_logic;
 204                        READ_XX3_2 : Out std_logic;
 205                        READ_XX5_4 : Out std_logic;
 206                        READ_XX7_6 : Out std_logic;
 207                        REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
 208                        REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
 209                        REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
 210                        TRDYn : Out std_logic;
 211                        WRITE_XX1_0 : Out std_logic;
 212                        WRITE_XX3_2 : Out std_logic;
 213                        WRITE_XX5_4 : Out std_logic;
 214                        WRITE_XX7_6 : Out std_logic );
 215         end component;
 216
 217         component dhwk_fifo
 218                 port (
 219                              clk: IN std_logic;
 220                              din: IN std_logic_VECTOR(7 downto 0);
 221                              rd_en: IN std_logic;
 222                              rst: IN std_logic;
 223                              wr_en: IN std_logic;
 224                              almost_empty: OUT std_logic;
 225                              almost_full: OUT std_logic;
 226                              dout: OUT std_logic_VECTOR(7 downto 0);
 227                              empty: OUT std_logic;
 228                              full: OUT std_logic;
 229                              prog_full: OUT std_logic);
 230         end component;
 231
 232         component icon
 233                 port
 234                 (
 235                         control0 : out std_logic_vector(35 downto 0)
 236                 );
 237         end component;
 238
 239         component ila
 240                 port
 241                 (
 242                         control : in std_logic_vector(35 downto 0);
 243                         clk : in std_logic;
 244                         data : in std_logic_vector(95 downto 0);
 245                         trig0 : in std_logic_vector(31 downto 0)
 246                 );
 247         end component;
 248
 249
 250 begin
 251         watch_PCI_REQn <= '1';
 252         SERIAL_IN <= SERIAL_OUT;
 253         SPC_RDY_IN <= SPC_RDY_OUT;
 254         LED_2 <= not PCI_RSTn;
 255         LED_3 <= PCI_IDSEL;
 256         LED_4 <= not PCI_FRAMEn;
 257         LED_5 <= not watch_PCI_INTAn;
 258         PCI_INTAn <= watch_PCI_INTAn;
 259         trig0(31 downto 0) <= (
 260         0 => watch_PCI_INTAn,
 261         1 => R_FIFO_READn,
 262         2 => R_FIFO_WRITEn,
 263         3 => S_FIFO_READn,
 264         4 => S_FIFO_WRITEn,
 265         5 => PCI_RSTn,
 266         16 => PCI_AD(0),
 267         17 => PCI_AD(1),
 268         18 => PCI_AD(2),
 269         19 => PCI_AD(3),
 270         20 => PCI_AD(4),
 271         21 => PCI_AD(5),
 272         22 => PCI_AD(6),
 273         23 => PCI_AD(7),
 274         27 => PCI_FRAMEn,
 275         28 => PCI_CBEn(0),
 276         29 => PCI_CBEn(1),
 277         30 => PCI_CBEn(2),
 278         31 => PCI_CBEn(3),
 279         others => '0');
 280
 281         data(0) <= watch_PCI_INTAn;
 282         data(1) <= R_EFn;
 283         data(2) <= R_HFn;
 284         data(3) <= R_FFn;
 285         data(4) <= R_FIFO_READn;
 286         data(5) <= R_FIFO_RESETn;
 287         data(6) <= R_FIFO_RTn;
 288         data(7) <= R_FIFO_WRITEn;
 289         data(8) <= S_EFn;
 290         data(9) <= S_HFn;
 291         data(10) <= S_FFn;
 292         data(11) <= S_FIFO_READn;
 293         data(12) <= S_FIFO_RESETn;
 294         data(13) <= S_FIFO_RTn;
 295         data(14) <= S_FIFO_WRITEn;
 296         data(15) <= SERIAL_IN;
 297         data(16) <= SPC_RDY_IN;
 298         data(17) <= SERIAL_OUT;
 299         data(18) <= SPC_RDY_OUT;
 300         data(26 downto 19) <= S_FIFO_Q_OUT;
 301         data(34 downto 27) <= R_FIFO_Q_OUT;
 302         data(66 downto 35) <= PCI_AD(31 downto 0);
 303         data(70 downto 67) <= PCI_CBEn(3 downto 0);
 304         data(71) <= PCI_FRAMEn;
 305         data(72) <= PCI_IDSEL;
 306         PCI_TRDYn <= watch_PCI_TRDYn;
 307         data(73) <= watch_PCI_TRDYn;
 308         data(74) <= PCI_IRDYn;
 309         PCI_STOPn <= watch_PCI_STOPn;
 310         data(75) <= watch_PCI_STOPn;
 311         PCI_SERRn <= watch_PCI_SERRn;
 312         data(76) <= watch_PCI_SERRn;
 313         PCI_PERRn <= watch_PCI_PERRn;
 314         data(77) <= watch_PCI_PERRn;
 315         PCI_REQn <= watch_PCI_REQn;
 316         data(78) <= watch_PCI_REQn;
 317         data(79) <= PCI_GNTn;
 318
 319         I19 : MESS_1_TB
 320         Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
 321                    PCI_IDSEL=>PCI_IDSEL,
 322                    REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
 323                    TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
 324                    TB_PCI_IDSEL=>TB_IDSEL );
 325         I18 : VEN_REV_ID
 326         Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
 327         VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
 328         I16 : INTERRUPT
 329         Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
 330                    INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
 331                    INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
 332                    INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
 333                    INT_RES(7 downto 0)=>AD_REG(7 downto 0),
 334                    PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
 335                    READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
 336                    TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
 337                    TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
 338                    INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
 339         I14 : FIFO_CONTROL
 340         Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
 341                    FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
 342                    PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
 343                    R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
 344                    RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
 345                    S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 346                    S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
 347                    SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
 348                    WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
 349                    R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
 350                    R_FIFO_READn=>R_FIFO_READn,
 351                    R_FIFO_RESETn=>R_FIFO_RESETn,
 352                    R_FIFO_RETRANSMITn=>R_FIFO_RTn,
 353                    R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
 354                    S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
 355                    S_FIFO_RESETn=>S_FIFO_RESETn,
 356                    S_FIFO_RETRANSMITn=>S_FIFO_RTn,
 357                    S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
 358                    SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
 359                    SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
 360         I1 : PCI_TOP
 361         Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
 362         INT_REG(7 downto 0)=>INT_REG(7 downto 0),
 363         PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
 364         PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
 365         PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
 366         PCI_RSTn=>PCI_RSTn,
 367         R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
 368         REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
 369         VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
 370         PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
 371         PCI_PAR=>PCI_PAR,
 372         AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 373         DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
 374         PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
 375         PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
 376         PCI_TRDYn=>watch_PCI_TRDYn,
 377         READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
 378         READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
 379         READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
 380         REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
 381         REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
 382         REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
 383         TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
 384         WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
 385         WRITE_XX7_6=>WRITE_XX7_6 );
 386
 387         receive_fifo : dhwk_fifo
 388         port map (
 389                          clk => PCI_CLOCK,
 390                          din => R_FIFO_D_IN,
 391                          rd_en => not R_FIFO_READn,
 392                          rst => not R_FIFO_RESETn,
 393                          wr_en => not R_FIFO_WRITEn,
 394                          dout => R_FIFO_Q_OUT,
 395                          empty => R_EFn,
 396                          full => R_FFn,
 397                          prog_full => R_HFn);
 398
 399         send_fifo : dhwk_fifo
 400         port map (
 401                          clk => PCI_CLOCK,
 402                          din => S_FIFO_D_IN,
 403                          rd_en => not S_FIFO_READn,
 404                          rst => not S_FIFO_RESETn,
 405                          wr_en => not S_FIFO_WRITEn,
 406                          dout => S_FIFO_Q_OUT,
 407                          empty => S_EFn,
 408                          full => S_FFn,
 409                          prog_full => S_HFn);
 410
 411         i_icon : icon
 412         port map
 413         (
 414                 control0 => control0
 415         );
 416
 417         i_ila : ila
 418         port map
 419         (
 420                 control => control0,
 421                 clk => PCI_CLOCK,
 422                 data => data,
 423                 trig0 => trig0
 424         );
 425 end SCHEMATIC;