cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/MESS_1_TB.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 29.08.2006
   4 -- File: MESS_1_TB.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity MESS_1_TB is
  10         port
  11         (
  12                 KONST_1 :in std_logic;
  13                 PCI_IDSEL :in std_logic;
  14                 DEVSELn :in std_logic;
  15                 INTAn :in std_logic;
  16                 REG_OUT_XX7 :in std_logic_vector(7 downto 0);
  17                 TB_PCI_IDSEL :out std_logic;
  18                 TB_DEVSELn :out std_logic;
  19                 TB_INTAn :out std_logic
  20         );
  21 end entity MESS_1_TB;
  22
  23 architecture MESS_1_TB_DESIGN of MESS_1_TB is
  24
  25 begin
  26
  27         TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
  28
  29         TB_INTAn <= INTAn and KONST_1;
  30
  31         TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
  32
  33 end architecture MESS_1_TB_DESIGN;