cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/steuerung.vhd

   1 -- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007
   2
   3 -- LIBRARY vanmacro;
   4 -- USE vanmacro.components.ALL;
   5 LIBRARY ieee;
   6 --LIBRARY generics;
   7 USE ieee.std_logic_1164.ALL;
   8 USE ieee.numeric_std.ALL;
   9 --USE generics.components.ALL;
  10
  11 entity STEUERUNG is
  12       Port (  AD_REG : In    std_logic_vector (31 downto 0);
  13              CBE_REGn : In    std_logic_vector (3 downto 0);
  14              FRAME_REGn : In    std_logic;
  15              IDSEL_REG : In    std_logic;
  16              IO_SPACE : In    std_logic;
  17              MY_ADDR : In    std_logic;
  18              PCI_CLOCK : In    std_logic;
  19              PCI_RSTn : In    std_logic;
  20              READ_FIFO : In    std_logic;
  21              CF_RD_COM : Out   std_logic;
  22              CF_WR_COM : Out   std_logic;
  23              DEVSELn : Out   std_logic;
  24              FIFO_RDn : Out   std_logic;
  25              IO_RD_COM : Out   std_logic;
  26              IO_WR_COM : Out   std_logic;
  27                  LAR : Out   std_logic;
  28              OE_PCI_PAR : Out   std_logic;
  29              OE_PCI_PERR : Out   std_logic;
  30              PCI_DEVSELn : Out   std_logic;
  31              PCI_STOPn : Out   std_logic;
  32              PCI_TRDYn : Out   std_logic;
  33              PERR_CHECK : Out   std_logic;
  34                 READ : Out   std_logic;
  35              SERR_CHECK : Out   std_logic;
  36                TRDYn : Out   std_logic );
  37 end STEUERUNG;
  38
  39 architecture SCHEMATIC of STEUERUNG is
  40
  41    SIGNAL gnd : std_logic := '0';
  42    SIGNAL vcc : std_logic := '1';
  43
  44    signal DEVSELn_DUMMY : std_logic;
  45    signal  IO_READ : std_logic;
  46    signal IO_WRITE : std_logic;
  47    signal CONF_READ : std_logic;
  48    signal CONF_WRITE : std_logic;
  49
  50    component CONT_FSM
  51       Port ( CONF_READ : In    std_logic;
  52              CONF_WRITE : In    std_logic;
  53              FIFO_READ : In    std_logic;
  54              IO_READ : In    std_logic;
  55              IO_WRITE : In    std_logic;
  56              PCI_CLOCK : In    std_logic;
  57              PCI_RSTn : In    std_logic;
  58              DEVSELn : Out   std_logic;
  59              FIFO_RDn : Out   std_logic;
  60              OE_PCI_PAR : Out   std_logic;
  61              OE_PCI_PERR : Out   std_logic;
  62              PCI_DEVSELn : Out   std_logic;
  63              PCI_STOPn : Out   std_logic;
  64              PCI_TRDYn : Out   std_logic;
  65              PERR_CHECK : Out   std_logic;
  66                 READ : Out   std_logic;
  67                TRDYn : Out   std_logic );
  68    end component;
  69
  70    component COMM_FSM
  71       Port ( CONF_READ : In    std_logic;
  72              CONF_WRITE : In    std_logic;
  73              DEVSELn : In    std_logic;
  74              IO_READ : In    std_logic;
  75              IO_WRITE : In    std_logic;
  76              PCI_CLOCK : In    std_logic;
  77              PCI_RSTn : In    std_logic;
  78              CF_RD_COM : Out   std_logic;
  79              CF_WR_COM : Out   std_logic;
  80              IO_RD_COM : Out   std_logic;
  81              IO_WR_COM : Out   std_logic );
  82    end component;
  83
  84    component COMM_DEC
  85       Port (  AD_REG : In    std_logic_vector (31 downto 0);
  86              CBE_REGn : In    std_logic_vector (3 downto 0);
  87              FRAME_REGn : In    std_logic;
  88              IDSEL_REG : In    std_logic;
  89              IO_SPACE : In    std_logic;
  90              MY_ADDR : In    std_logic;
  91              PCI_CLOCK : In    std_logic;
  92              PCI_RSTn : In    std_logic;
  93              CONF_READ : Out   std_logic;
  94              CONF_WRITE : Out   std_logic;
  95              IO_READ : Out   std_logic;
  96              IO_WRITE : Out   std_logic;
  97                  LAR : Out   std_logic;
  98              SERR_CHECK : Out   std_logic );
  99    end component;
 100
 101 begin
 102
 103    DEVSELn <= DEVSELn_DUMMY;
 104
 105    I1 : CONT_FSM
 106       Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
 107                  FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
 108                  IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
 109                  PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
 110                  FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
 111                  OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
 112                  PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
 113                  PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
 114    I2 : COMM_FSM
 115       Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
 116                  DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
 117                  IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
 118                  PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
 119                  CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
 120                  IO_WR_COM=>IO_WR_COM );
 121    I3 : COMM_DEC
 122       Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 123                  CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 124                  FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
 125                  IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
 126                  PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
 127                  CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
 128                  IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
 129                  SERR_CHECK=>SERR_CHECK );
 130
 131 end SCHEMATIC;