cvs.zerfleddert.de Git - raggedstone/blob - dhwk

1 --+-------------------------------------------------------------------------------------------------+

2 --| |

3 --| File: pcipargen.vhd |

4 --| |

5 --| Project: pci32tlite_oc |

6 --| |

7 --| Description: PCI Parity Generator. |

8 --| PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD, |

9 --| CBE and PAR is even. |

10 --| |

11 --+-------------------------------------------------------------------------------------------------+

12 --| |

13 --| Revision history : |

14 --| Date Version Author Description |

15 --| 2005-05-13 R00A00 PAU First alfa revision (eng) |

16 --| |

17 --| To do: |

18 --| |

19 --+-------------------------------------------------------------------------------------------------+

20 --+-----------------------------------------------------------------+

21 --| |

23 --| |

24 --| This source file may be used and distributed without |

25 --| restriction provided that this copyright statement is not |

26 --| removed from the file and that any derivative work contains |

27 --| the original copyright notice and the associated disclaimer. |

28 --| |

29 --| This source file is free software; you can redistribute it |

30 --| and/or modify it under the terms of the GNU Lesser General |

31 --| Public License as published by the Free Software Foundation; |

32 --| either version 2.1 of the License, or (at your option) any |

33 --| later version. |

34 --| |

35 --| This source is distributed in the hope that it will be |

36 --| useful, but WITHOUT ANY WARRANTY; without even the implied |

37 --| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |

38 --| PURPOSE. See the GNU Lesser General Public License for more |

39 --| details. |

40 --| |

41 --| You should have received a copy of the GNU Lesser General |

42 --| Public License along with this source; if not, download it |

43 --| from http://www.opencores.org/lgpl.shtml |

44 --| |

45 --+-----------------------------------------------------------------+

46

47

48 --+-----------------------------------------------------------------------------+

49 --| LIBRARIES |

50 --+-----------------------------------------------------------------------------+

51

52 library ieee;

53 use ieee.std_logic_1164.all;

54

55

56

57 --+-----------------------------------------------------------------------------+

58 --| ENTITY |

59 --+-----------------------------------------------------------------------------+

60

61 entity pcipargen is

62 port (

63

64 clk_i : in std_logic;

65 pcidatout_i : in std_logic_vector(31 downto 0);

66 cbe_i : in std_logic_vector(3 downto 0);

67 parOE_i : in std_logic;

68 par_o : out std_logic

69

70 );

71 end pcipargen;

72

73

74 architecture rtl of pcipargen is

75

76

77 --+-----------------------------------------------------------------------------+

78 --| COMPONENTS |

79 --+-----------------------------------------------------------------------------+

80 --+-----------------------------------------------------------------------------+

81 --| CONSTANTS |

82 --+-----------------------------------------------------------------------------+

83 --+-----------------------------------------------------------------------------+

84 --| SIGNALS |

85 --+-----------------------------------------------------------------------------+

86

87 signal d : std_logic_vector(31 downto 0);

88 signal pardat : std_logic;

89 signal parcbe : std_logic;

90 signal par : std_logic;

91 signal par_s : std_logic;

92

93 component sync

94 port (

95 clk : in std_logic;

96 d : in std_logic;

97 q : out std_logic

98 );

99 end component;

100

101 component sync2

102 port (

103 clk : in std_logic;

104 d : in std_logic;

105 q : out std_logic

106 );

107 end component;

108

109 begin

110

111

112 d <= pcidatout_i;

113

114

115 --+-------------------------------------------------------------------------+

116 --| building parity |

117 --+-------------------------------------------------------------------------+

118

119 pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor

120 d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor

121 d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor

122 d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);

123

124 parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3);

125

126 par <= pardat xor parcbe;

127

128 -- u1: sync port map ( clk => clk_i, d => par, q => par_s );

129

130 u1: sync2 port map (

131 clk => clk_i,

132 d => par,

133 q => par_s

134 );

135

136

137 --+-------------------------------------------------------------------------+

138 --| PAR |

139 --+-------------------------------------------------------------------------+

140

141 par_o <= par_s when ( parOE_i = '1' ) else 'Z';

142

143

144 end rtl;