cvs.zerfleddert.de Git - raggedstone/blob - dhwk_old/source/top

1 library ieee;

2 use ieee.std_logic_1164.all;

3 use ieee.std_logic_arith.all;

4 use ieee.std_logic_unsigned.all;

6 entity dhwk is

7 port (

9 -- General

10 PCI_CLK : in std_logic;

11 PCI_nRES : in std_logic;

13 -- PCI target 32bits

14 PCI_AD : inout std_logic_vector(31 downto 0);

15 PCI_CBE : in std_logic_vector(3 downto 0);

16 PCI_PAR : out std_logic;

17 PCI_nFRAME : in std_logic;

18 PCI_nIRDY : in std_logic;

19 PCI_nTRDY : out std_logic;

20 PCI_nDEVSEL : out std_logic;

21 PCI_nSTOP : out std_logic;

22 PCI_IDSEL : in std_logic;

23 PCI_nPERR : out std_logic;

24 PCI_nSERR : out std_logic;

25 PCI_nINT : out std_logic;

27 -- debug signals

28 LED3 : out std_logic;

29 LED2 : out std_logic;

30 LED4 : out std_logic;

31 LED5 : out std_logic

33 );

34 end dhwk;

37 architecture dhwk_arch of dhwk is

40 component pci32tlite

41 port (

43 -- General

44 clk33 : in std_logic;

45 nrst : in std_logic;

47 -- PCI target 32bits

48 ad : inout std_logic_vector(31 downto 0);

49 cbe : in std_logic_vector(3 downto 0);

50 par : out std_logic;

51 frame : in std_logic;

52 irdy : in std_logic;

53 trdy : out std_logic;

54 devsel : out std_logic;

55 stop : out std_logic;

56 idsel : in std_logic;

57 perr : out std_logic;

58 serr : out std_logic;

59 intb : out std_logic;

61 -- Master whisbone

62 wb_adr_o : out std_logic_vector(24 downto 1);

63 wb_dat_i : in std_logic_vector(15 downto 0);

64 wb_dat_o : out std_logic_vector(15 downto 0);

65 wb_sel_o : out std_logic_vector(1 downto 0);

66 wb_we_o : out std_logic;

67 wb_stb_o : out std_logic;

68 wb_cyc_o : out std_logic;

69 wb_ack_i : in std_logic;

70 wb_err_i : in std_logic;

71 wb_int_i : in std_logic;

73 -- debug signals

74 debug_init : out std_logic;

75 debug_access : out std_logic

77 );

78 end component;

80 component heartbeat

81 port (

82 clk_i : in std_logic;

83 nrst_i : in std_logic;

84 led2_o : out std_logic;

85 led3_o : out std_logic;

86 led4_o : out std_logic;

87 led5_o : out std_logic

88 );

89 end component;

91 component generic_fifo_sc_a

92 port (

93 clk : in std_logic;

94 rst : in std_logic;

95 clr : in std_logic;

96 din : in std_logic_vector(7 downto 0);

97 we : in std_logic;

98 dout : out std_logic_vector(7 downto 0);

99 re : in std_logic;

100 full : out std_logic;

101 full_r : out std_logic;

102 empty : out std_logic;

103 empty_r : out std_logic;

104 full_n : out std_logic;

105 full_n_r : out std_logic;

106 empty_n : out std_logic;

107 empty_n_r : out std_logic;

108 level : out std_logic_vector(1 downto 0)

109 );

110 end component;

111

112 component wb_fifo

113 port (

114 clk_i : in std_logic;

115 nrst_i : in std_logic;

116

117 wb_adr_i : in std_logic_vector(24 downto 1);

118 wb_dat_o : out std_logic_vector(15 downto 0);

119 wb_dat_i : in std_logic_vector(15 downto 0);

120 wb_sel_i : in std_logic_vector(1 downto 0);

121 wb_we_i : in std_logic;

122 wb_stb_i : in std_logic;

123 wb_cyc_i : in std_logic;

124 wb_ack_o : out std_logic;

125 wb_err_o : out std_logic;

126 wb_int_o : out std_logic;

127

128 fifo_data_i : in std_logic_vector(7 downto 0);

129 fifo_data_o : out std_logic_vector(7 downto 0);

130

131 fifo_we_o : out std_logic;

132 fifo_re_o : out std_logic

133 );

134 end component;

135

136 signal wb_adr : std_logic_vector(24 downto 1);

137 signal wb_dat_out : std_logic_vector(15 downto 0);

138 signal wb_dat_in : std_logic_vector(15 downto 0);

139 signal wb_sel : std_logic_vector(1 downto 0);

140 signal wb_we : std_logic;

141 signal wb_stb : std_logic;

142 signal wb_cyc : std_logic;

143 signal wb_ack : std_logic;

144 signal wb_err : std_logic;

145 signal wb_int : std_logic;

146

147 signal fifo_din : std_logic_vector(7 downto 0);

148 signal fifo_dout : std_logic_vector(7 downto 0);

149 signal fifo_we : std_logic;

150 signal fifo_re : std_logic;

154 begin

156 u_pci: component pci32tlite

157 port map(

158 clk33 => PCI_CLK,

159 nrst => PCI_nRES,

160 ad => PCI_AD,

161 cbe => PCI_CBE,

162 par => PCI_PAR,

163 frame => PCI_nFRAME,

164 irdy => PCI_nIRDY,

165 trdy => PCI_nTRDY,

166 devsel => PCI_nDEVSEL,

167 stop => PCI_nSTOP,

168 idsel => PCI_IDSEL,

169 perr => PCI_nPERR,

170 serr => PCI_nSERR,

171 intb => PCI_nINT,

172 wb_adr_o => wb_adr,

173 wb_dat_i => wb_dat_out,

174 wb_dat_o => wb_dat_in,

175 wb_sel_o => wb_sel,

176 wb_we_o => wb_we,

177 wb_stb_o => wb_stb,

178 wb_cyc_o => wb_cyc,

179 wb_ack_i => wb_ack,

180 wb_err_i => wb_err,

181 wb_int_i => wb_int

182 -- debug_init => LED3,

183 -- debug_access => LED2

184 );

185

186 my_generic_fifo: component generic_fifo_sc_a

187 port map(

188 clk => PCI_CLK,

189 rst => PCI_nRES,

190 clr => '0',

191 din => fifo_din,

192 we => fifo_we,

193 dout => fifo_dout,

194 re => fifo_re

195 -- full => ,

196 -- full_r => ,

197 -- empty => ,

198 -- empty_r => ,

199 -- full_n => ,

200 -- full_n_r => ,

201 -- empty_n => ,

202 -- empty_n_r => ,

203 -- level => ,

204 );

205

206 my_fifo: component wb_fifo

207 port map(

208 clk_i => PCI_CLK,

209 nrst_i => PCI_nRES,

210

211 wb_adr_i => wb_adr,

212 wb_dat_o => wb_dat_out,

213 wb_dat_i => wb_dat_in,

214 wb_sel_i => wb_sel,

215 wb_we_i => wb_we,

216 wb_stb_i => wb_stb,

217 wb_cyc_i => wb_cyc,

218 wb_ack_o => wb_ack,

219 wb_err_o => wb_err,

220 wb_int_o => wb_int,

221

222 fifo_data_i => fifo_dout,

223 fifo_data_o => fifo_din,

224

225 fifo_we_o => fifo_we,

226 fifo_re_o => fifo_re

227 );

228

229 my_heartbeat: component heartbeat

230 port map(

231 clk_i => PCI_CLK,

232 nrst_i => PCI_nRES,

233 led2_o => LED2,

234 led3_o => LED3,

235 led4_o => LED4,

236 led5_o => LED5

237 );

238

239 end dhwk_arch;