cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci

1 //////////////////////////////////////////////////////////////////////

2 //// ////

3 //// File name "pci_constants.v" ////

4 //// ////

5 //// This file is part of the "PCI bridge" project ////

6 //// http://www.opencores.org/cores/pci/ ////

7 //// ////

8 //// Author(s): ////

9 //// - Miha Dolenc (mihad@opencores.org) ////

10 //// - Tadej Markovic (tadej@opencores.org) ////

11 //// ////

12 //// All additional information is avaliable in the README.txt ////

13 //// file. ////

14 //// ////

15 //// ////

16 //////////////////////////////////////////////////////////////////////

17 //// ////

19 //// ////

20 //// This source file may be used and distributed without ////

21 //// restriction provided that this copyright statement is not ////

22 //// removed from the file and that any derivative work contains ////

23 //// the original copyright notice and the associated disclaimer. ////

24 //// ////

25 //// This source file is free software; you can redistribute it ////

26 //// and/or modify it under the terms of the GNU Lesser General ////

27 //// Public License as published by the Free Software Foundation; ////

28 //// either version 2.1 of the License, or (at your option) any ////

29 //// later version. ////

30 //// ////

31 //// This source is distributed in the hope that it will be ////

32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////

33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

34 //// PURPOSE. See the GNU Lesser General Public License for more ////

35 //// details. ////

36 //// ////

37 //// You should have received a copy of the GNU Lesser General ////

38 //// Public License along with this source; if not, download it ////

39 //// from http://www.opencores.org/lgpl.shtml ////

40 //// ////

41 //////////////////////////////////////////////////////////////////////

42 //

43 // CVS Revision History

44 //

45 // $Log: pci_constants.v,v $

46 // Revision 1.1 2007-03-20 17:50:56 sithglan

47 // add shit

48 //

49 // Revision 1.2 2003/12/19 11:11:30 mihad

50 // Compact PCI Hot Swap support added.

51 // New testcases added.

52 // Specification updated.

53 // Test application changed to support WB B3 cycles.

54 //

55 // Revision 1.1 2002/02/01 14:43:31 mihad

56 // *** empty log message ***

57 //

58 // Revision 1.2 2001/10/05 08:14:28 mihad

59 // Updated all files with inclusion of timescale file for simulation purposes.

60 //

61 // Revision 1.1.1.1 2001/10/02 15:33:46 mihad

62 // New project directory structure

63 //

64

65 // first include user definable parameters

66 `ifdef REGRESSION // Used only for regression testing purposes!!!

67 `include "pci_regression_constants.v"

68 `else

69 `include "pci_user_constants.v"

70 `endif

71

72 ////////////////////////////////////////////////////////////////////////

73 //// ////

74 //// FIFO parameters define behaviour of FIFO control logic and ////

75 //// FIFO depths. ////

76 //// ////

77 ////////////////////////////////////////////////////////////////////////

78 `define WBW_DEPTH (1 << `WBW_ADDR_LENGTH)

79 `define WBR_DEPTH (1 << `WBR_ADDR_LENGTH)

80 `define PCIW_DEPTH (1 << `PCIW_ADDR_LENGTH)

81 `define PCIR_DEPTH (1 << `PCIR_ADDR_LENGTH)

82

83 // defines on which bit in control bus means what

84 `define ADDR_CTRL_BIT 3

85 `define LAST_CTRL_BIT 0

86 `define DATA_ERROR_CTRL_BIT 1

87 `define UNUSED_CTRL_BIT 2

88 `define BURST_BIT 2

89

90 // MAX Retry counter value for PCI Master state-machine

91 // This value is 8-bit because of 8-bit retry counter !!!

92 //`define PCI_RTY_CNT_MAX 8'h08

93

94 // Value of address mask for WB configuration image. This has to be defined always, since it is a value, that is not changable in runtime.

95 // !!!!!!!!!!!!!!!!!!!!!!!If this is not defined, WB configuration access will not be possible!!!!!!!!!!!!!!!!!!!!!1

96 `define WB_AM0 20'hffff_f

97

98 // PCI target & WB slave ADDRESS names for configuration space !!!

99 // This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)

100 // ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while

101 // accessing this registers, otherwise the configuration header will be accessed !!!

102 `define PCI_CAP_PTR_VAL 8'h80

103 `define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100

104 `define P_BA0_ADDR 6'h01 // Address offset = h 104

105 `define P_AM0_ADDR 6'h02 // Address offset = h 108

106 `define P_TA0_ADDR 6'h03 // Address offset = h 10c

107 `define P_IMG_CTRL1_ADDR 6'h04 // Address offset = h 110

108 `define P_BA1_ADDR 6'h05 // Address offset = h 114

109 `define P_AM1_ADDR 6'h06 // Address offset = h 118

110 `define P_TA1_ADDR 6'h07 // Address offset = h 11c

111 `define P_IMG_CTRL2_ADDR 6'h08 // Address offset = h 120

112 `define P_BA2_ADDR 6'h09 // Address offset = h 124

113 `define P_AM2_ADDR 6'h0a // Address offset = h 128

114 `define P_TA2_ADDR 6'h0b // Address offset = h 12c

115 `define P_IMG_CTRL3_ADDR 6'h0c // Address offset = h 130

116 `define P_BA3_ADDR 6'h0d // Address offset = h 134

117 `define P_AM3_ADDR 6'h0e // Address offset = h 138

118 `define P_TA3_ADDR 6'h0f // Address offset = h 13c

119 `define P_IMG_CTRL4_ADDR 6'h10 // Address offset = h 140

120 `define P_BA4_ADDR 6'h11 // Address offset = h 144

121 `define P_AM4_ADDR 6'h12 // Address offset = h 148

122 `define P_TA4_ADDR 6'h13 // Address offset = h 14c

123 `define P_IMG_CTRL5_ADDR 6'h14 // Address offset = h 150

124 `define P_BA5_ADDR 6'h15 // Address offset = h 154

125 `define P_AM5_ADDR 6'h16 // Address offset = h 158

126 `define P_TA5_ADDR 6'h17 // Address offset = h 15c

127 `define P_ERR_CS_ADDR 6'h18 // Address offset = h 160

128 `define P_ERR_ADDR_ADDR 6'h19 // Address offset = h 164

129 `define P_ERR_DATA_ADDR 6'h1a // Address offset = h 168

130

131 `define WB_CONF_SPC_BAR_ADDR 6'h20 // Address offset = h 180

132 `define W_IMG_CTRL1_ADDR 6'h21 // Address offset = h 184

133 `define W_BA1_ADDR 6'h22 // Address offset = h 188

134 `define W_AM1_ADDR 6'h23 // Address offset = h 18c

135 `define W_TA1_ADDR 6'h24 // Address offset = h 190

136 `define W_IMG_CTRL2_ADDR 6'h25 // Address offset = h 194

137 `define W_BA2_ADDR 6'h26 // Address offset = h 198

138 `define W_AM2_ADDR 6'h27 // Address offset = h 19c

139 `define W_TA2_ADDR 6'h28 // Address offset = h 1a0

140 `define W_IMG_CTRL3_ADDR 6'h29 // Address offset = h 1a4

141 `define W_BA3_ADDR 6'h2a // Address offset = h 1a8

142 `define W_AM3_ADDR 6'h2b // Address offset = h 1ac

143 `define W_TA3_ADDR 6'h2c // Address offset = h 1b0

144 `define W_IMG_CTRL4_ADDR 6'h2d // Address offset = h 1b4

145 `define W_BA4_ADDR 6'h2e // Address offset = h 1b8

146 `define W_AM4_ADDR 6'h2f // Address offset = h 1bc

147 `define W_TA4_ADDR 6'h30 // Address offset = h 1c0

148 `define W_IMG_CTRL5_ADDR 6'h31 // Address offset = h 1c4

149 `define W_BA5_ADDR 6'h32 // Address offset = h 1c8

150 `define W_AM5_ADDR 6'h33 // Address offset = h 1cc

151 `define W_TA5_ADDR 6'h34 // Address offset = h 1d0

152 `define W_ERR_CS_ADDR 6'h35 // Address offset = h 1d4

153 `define W_ERR_ADDR_ADDR 6'h36 // Address offset = h 1d8

154 `define W_ERR_DATA_ADDR 6'h37 // Address offset = h 1dc

155 `define CNF_ADDR_ADDR 6'h38 // Address offset = h 1e0

156 // Following two registers are not implemented in a configuration space but in a WishBone unit!

157 `define CNF_DATA_ADDR 6'h39 // Address offset = h 1e4

158 `define INT_ACK_ADDR 6'h3a // Address offset = h 1e8

159 // -------------------------------------

160 `define ICR_ADDR 6'h3b // Address offset = h 1ec

161 `define ISR_ADDR 6'h3c // Address offset = h 1f0

162

163 `ifdef PCI33

164 `define HEADER_66MHz 1'b0

165 `else

166 `ifdef PCI66

167 `define HEADER_66MHz 1'b1

168 `endif

169 `endif

170

171 // all flip-flops in the design have this inter-assignment delay

172 `define FF_DELAY 1

173