cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_target

1 //////////////////////////////////////////////////////////////////////

2 //// ////

3 //// File name: pci_target_unit.v ////

4 //// ////

5 //// This file is part of the "PCI bridge" project ////

6 //// http://www.opencores.org/cores/pci/ ////

7 //// ////

8 //// Author(s): ////

9 //// - Tadej Markovic, tadej@opencores.org ////

10 //// ////

11 //// All additional information is avaliable in the README.txt ////

12 //// file. ////

13 //// ////

14 //// ////

15 //////////////////////////////////////////////////////////////////////

16 //// ////

18 //// ////

19 //// This source file may be used and distributed without ////

20 //// restriction provided that this copyright statement is not ////

21 //// removed from the file and that any derivative work contains ////

22 //// the original copyright notice and the associated disclaimer. ////

23 //// ////

24 //// This source file is free software; you can redistribute it ////

25 //// and/or modify it under the terms of the GNU Lesser General ////

26 //// Public License as published by the Free Software Foundation; ////

27 //// either version 2.1 of the License, or (at your option) any ////

28 //// later version. ////

29 //// ////

30 //// This source is distributed in the hope that it will be ////

31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////

32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

33 //// PURPOSE. See the GNU Lesser General Public License for more ////

34 //// details. ////

35 //// ////

36 //// You should have received a copy of the GNU Lesser General ////

37 //// Public License along with this source; if not, download it ////

38 //// from http://www.opencores.org/lgpl.shtml ////

39 //// ////

40 //////////////////////////////////////////////////////////////////////

41 //

42 // CVS Revision History

43 //

44 // $Log: pci_target_unit.v,v $

45 // Revision 1.1 2007-03-20 17:50:56 sithglan

46 // add shit

47 //

48 // Revision 1.16 2004/08/19 15:27:34 mihad

49 // Changed minimum pci image size to 256 bytes because

50 // of some PC system problems with size of IO images.

51 //

52 // Revision 1.15 2003/12/19 11:11:30 mihad

53 // Compact PCI Hot Swap support added.

54 // New testcases added.

55 // Specification updated.

56 // Test application changed to support WB B3 cycles.

57 //

58 // Revision 1.14 2003/10/17 09:11:52 markom

59 // mbist signals updated according to newest convention

60 //

61 // Revision 1.13 2003/08/21 20:55:14 tadejm

62 // Corrected bug when writing to FIFO (now it is registered).

63 //

64 // Revision 1.12 2003/08/08 16:36:33 tadejm

65 // Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.

66 //

67 // Revision 1.11 2003/01/27 16:49:31 mihad

68 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.

69 //

70 // Revision 1.10 2002/10/18 03:36:37 tadejm

71 // Changed wrong signal name mbist_sen into mbist_ctrl_i.

72 //

73 // Revision 1.9 2002/10/17 22:51:08 tadejm

74 // Changed BIST signals for RAMs.

75 //

76 // Revision 1.8 2002/10/11 10:09:01 mihad

77 // Added additional testcase and changed rst name in BIST to trst

78 //

79 // Revision 1.7 2002/10/08 17:17:05 mihad

80 // Added BIST signals for RAMs.

81 //

82 // Revision 1.6 2002/09/25 15:53:52 mihad

83 // Removed all logic from asynchronous reset network

84 //

85 // Revision 1.5 2002/03/05 11:53:47 mihad

86 // Added some testcases, removed un-needed fifo signals

87 //

88 // Revision 1.4 2002/02/19 16:32:37 mihad

89 // Modified testbench and fixed some bugs

90 //

91 // Revision 1.3 2002/02/01 15:25:13 mihad

92 // Repaired a few bugs, updated specification, added test bench files and design document

93 //

94 // Revision 1.2 2001/10/05 08:14:30 mihad

95 // Updated all files with inclusion of timescale file for simulation purposes.

96 //

97 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad

98 // New project directory structure

99 //

100 //

101

102 // Module instantiates and connects other modules lower in hierarcy

103 // PCI target unit consists of modules that together form datapath

104 // between external WISHBONE slaves and external PCI initiators

105 `include "pci_constants.v"

106

107 // synopsys translate_off

108 `include "timescale.v"

109 // synopsys translate_on

110

111 module pci_target_unit

112 (

113 reset_in,

114 wb_clock_in,

115 pci_clock_in,

116

117 pciu_wbm_adr_o,

118 pciu_wbm_dat_o,

119 pciu_wbm_dat_i,

120 pciu_wbm_cyc_o,

121 pciu_wbm_stb_o,

122 pciu_wbm_we_o,

123 pciu_wbm_cti_o,

124 pciu_wbm_bte_o,

125 pciu_wbm_sel_o,

126 pciu_wbm_ack_i,

127 pciu_wbm_rty_i,

128 pciu_wbm_err_i,

129 pciu_mem_enable_in,

130 pciu_io_enable_in,

131 pciu_map_in,

132 pciu_pref_en_in,

133 pciu_conf_data_in,

134 pciu_wbw_fifo_empty_in,

135 pciu_wbu_del_read_comp_pending_in,

136 pciu_wbu_frame_en_in,

137 pciu_bar0_in,

138 pciu_bar1_in,

139 pciu_bar2_in,

140 pciu_bar3_in,

141 pciu_bar4_in,

142 pciu_bar5_in,

143 pciu_am0_in,

144 pciu_am1_in,

145 pciu_am2_in,

146 pciu_am3_in,

147 pciu_am4_in,

148 pciu_am5_in,

149 pciu_ta0_in,

150 pciu_ta1_in,

151 pciu_ta2_in,

152 pciu_ta3_in,

153 pciu_ta4_in,

154 pciu_ta5_in,

155 pciu_at_en_in,

156 pciu_cache_line_size_in,

157 pciu_cache_lsize_not_zero_in,

158 pciu_pciif_frame_in,

159 pciu_pciif_irdy_in,

160 pciu_pciif_idsel_in,

161 pciu_pciif_frame_reg_in,

162 pciu_pciif_irdy_reg_in,

163 pciu_pciif_idsel_reg_in,

164 pciu_pciif_ad_reg_in,

165 pciu_pciif_cbe_reg_in,

166 pciu_pciif_cbe_in,

167 pciu_pciif_bckp_trdy_en_in,

168 pciu_pciif_bckp_devsel_in,

169 pciu_pciif_bckp_trdy_in,

170 pciu_pciif_bckp_stop_in,

171 pciu_pciif_trdy_reg_in,

172 pciu_pciif_stop_reg_in,

173 pciu_pciif_trdy_out,

174 pciu_pciif_stop_out,

175 pciu_pciif_devsel_out,

176 pciu_pciif_trdy_en_out,

177 pciu_pciif_stop_en_out,

178 pciu_pciif_devsel_en_out,

179 pciu_ad_load_out,

180 pciu_ad_load_on_transfer_out,

181 pciu_pciif_ad_out,

182 pciu_pciif_ad_en_out,

183 pciu_pciif_tabort_set_out,

184 pciu_err_addr_out,

185 pciu_err_bc_out,

186 pciu_err_data_out,

187 pciu_err_be_out,

188 pciu_err_signal_out,

189 pciu_err_source_out,

190 pciu_err_rty_exp_out,

191 pciu_conf_offset_out,

192 pciu_conf_renable_out,

193 pciu_conf_wenable_out,

194 pciu_conf_be_out,

195 pciu_conf_data_out,

196 pciu_pci_drcomp_pending_out,

197 pciu_pciw_fifo_empty_out

198

199 `ifdef PCI_BIST

200 ,

201 // debug chain signals

202 mbist_si_i, // bist scan serial in

203 mbist_so_o, // bist scan serial out

204 mbist_ctrl_i // bist chain shift control

205 `endif

206 );

207

208 `ifdef HOST

209 `ifdef NO_CNF_IMAGE

210 parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;

211 `else

212 parameter pci_ba0_width = 20 ;

213 `endif

214 `endif

215

216 `ifdef GUEST

217 parameter pci_ba0_width = 20 ;

218 `endif

219

220 parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;

221

222 input reset_in,

223 wb_clock_in,

224 pci_clock_in ;

225

226 output [31:0] pciu_wbm_adr_o ;

227 output [31:0] pciu_wbm_dat_o ;

228 input [31:0] pciu_wbm_dat_i ;

229 output pciu_wbm_cyc_o ;

230 output pciu_wbm_stb_o ;

231 output pciu_wbm_we_o ;

232 output [2:0] pciu_wbm_cti_o ;

233 output [1:0] pciu_wbm_bte_o ;

234 output [3:0] pciu_wbm_sel_o ;

235 input pciu_wbm_ack_i ;

236 input pciu_wbm_rty_i ;

237 input pciu_wbm_err_i ;

238

239 input pciu_wbw_fifo_empty_in ;

240 input pciu_wbu_del_read_comp_pending_in ;

241 input pciu_wbu_frame_en_in ;

242

243 input pciu_mem_enable_in ;

244 input pciu_io_enable_in ;

245 input [5:0] pciu_map_in ;

246 input [5:0] pciu_pref_en_in ;

247 input [31:0] pciu_conf_data_in ;

248

249 input [pci_ba0_width - 1:0] pciu_bar0_in ;

250 input [pci_ba1_5_width - 1:0] pciu_bar1_in ;

251 input [pci_ba1_5_width - 1:0] pciu_bar2_in ;

252 input [pci_ba1_5_width - 1:0] pciu_bar3_in ;

253 input [pci_ba1_5_width - 1:0] pciu_bar4_in ;

254 input [pci_ba1_5_width - 1:0] pciu_bar5_in ;

255 input [pci_ba1_5_width - 1:0] pciu_am0_in ;

256 input [pci_ba1_5_width - 1:0] pciu_am1_in ;

257 input [pci_ba1_5_width - 1:0] pciu_am2_in ;

258 input [pci_ba1_5_width - 1:0] pciu_am3_in ;

259 input [pci_ba1_5_width - 1:0] pciu_am4_in ;

260 input [pci_ba1_5_width - 1:0] pciu_am5_in ;

261 input [pci_ba1_5_width - 1:0] pciu_ta0_in ;

262 input [pci_ba1_5_width - 1:0] pciu_ta1_in ;

263 input [pci_ba1_5_width - 1:0] pciu_ta2_in ;

264 input [pci_ba1_5_width - 1:0] pciu_ta3_in ;

265 input [pci_ba1_5_width - 1:0] pciu_ta4_in ;

266 input [pci_ba1_5_width - 1:0] pciu_ta5_in ;

267 input [5:0] pciu_at_en_in ;

268

269 input [7:0] pciu_cache_line_size_in ;

270 input pciu_cache_lsize_not_zero_in ;

271

272 input pciu_pciif_frame_in ;

273 input pciu_pciif_irdy_in ;

274 input pciu_pciif_idsel_in ;

275 input pciu_pciif_frame_reg_in ;

276 input pciu_pciif_irdy_reg_in ;

277 input pciu_pciif_idsel_reg_in ;

278 input [31:0] pciu_pciif_ad_reg_in ;

279 input [3:0] pciu_pciif_cbe_reg_in ;

280 input [3:0] pciu_pciif_cbe_in;

281 input pciu_pciif_bckp_trdy_en_in ;

282 input pciu_pciif_bckp_devsel_in ;

283 input pciu_pciif_bckp_trdy_in ;

284 input pciu_pciif_bckp_stop_in ;

285 input pciu_pciif_trdy_reg_in ;

286 input pciu_pciif_stop_reg_in ;

287

288

289 output pciu_pciif_trdy_out ;

290 output pciu_pciif_stop_out ;

291 output pciu_pciif_devsel_out ;

292 output pciu_pciif_trdy_en_out ;

293 output pciu_pciif_stop_en_out ;

294 output pciu_pciif_devsel_en_out ;

295 output pciu_ad_load_out ;

296 output pciu_ad_load_on_transfer_out ;

297 output [31:0] pciu_pciif_ad_out ;

298 output pciu_pciif_ad_en_out ;

299 output pciu_pciif_tabort_set_out ;

300

301 output [31:0] pciu_err_addr_out ;

302 output [3:0] pciu_err_bc_out ;

303 output [31:0] pciu_err_data_out ;

304 output [3:0] pciu_err_be_out ;

305 output pciu_err_signal_out ;

306 output pciu_err_source_out ;

307 output pciu_err_rty_exp_out ;

308

309 output [11:0] pciu_conf_offset_out ;

310 output pciu_conf_renable_out ;

311 output pciu_conf_wenable_out ;

312 output [3:0] pciu_conf_be_out ;

313 output [31:0] pciu_conf_data_out ;

314

315 output pciu_pci_drcomp_pending_out ;

316 output pciu_pciw_fifo_empty_out ;

317

318 `ifdef PCI_BIST

319 /*-----------------------------------------------------

320 BIST debug chain port signals

321 -----------------------------------------------------*/

322 input mbist_si_i; // bist scan serial in

323 output mbist_so_o; // bist scan serial out

324 input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control

325 `endif

326

327

328 // pci target state machine and interface outputs

329 wire pcit_sm_trdy_out ;

330 wire pcit_sm_stop_out ;

331 wire pcit_sm_devsel_out ;

332 wire pcit_sm_trdy_en_out ;

333 wire pcit_sm_stop_en_out ;

334 wire pcit_sm_devsel_en_out ;

335 wire pcit_sm_ad_load_out ;

336 wire pcit_sm_ad_load_on_transfer_out ;

337 wire [31:0] pcit_sm_ad_out ;

338 wire pcit_sm_ad_en_out ;

339 wire [31:0] pcit_sm_address_out ;

340 wire [3:0] pcit_sm_bc_out ;

341 wire pcit_sm_bc0_out ;

342 wire [31:0] pcit_sm_data_out ;

343 wire [3:0] pcit_sm_be_out ;

344 wire [3:0] pcit_sm_next_be_out ;

345 wire pcit_sm_req_out ;

346 wire pcit_sm_rdy_out ;

347 wire pcit_sm_addr_phase_out ;

348 wire pcit_sm_bckp_devsel_out ;

349 wire pcit_sm_bckp_trdy_out ;

350 wire pcit_sm_bckp_stop_out ;

351 wire pcit_sm_last_reg_out ;

352 wire pcit_sm_frame_reg_out ;

353 wire pcit_sm_fetch_pcir_fifo_out ;

354 wire pcit_sm_load_medium_reg_out ;

355 wire pcit_sm_sel_fifo_mreg_out ;

356 wire pcit_sm_sel_conf_fifo_out ;

357 wire pcit_sm_load_to_pciw_fifo_out ;

358 wire pcit_sm_load_to_conf_out ;

359

360 wire pcit_sm_target_abort_set_out ; // to conf space

361

362 assign pciu_pciif_trdy_out = pcit_sm_trdy_out ;

363 assign pciu_pciif_stop_out = pcit_sm_stop_out ;

364 assign pciu_pciif_devsel_out = pcit_sm_devsel_out ;

365 assign pciu_pciif_trdy_en_out = pcit_sm_trdy_en_out ;

366 assign pciu_pciif_stop_en_out = pcit_sm_stop_en_out ;

367 assign pciu_pciif_devsel_en_out = pcit_sm_devsel_en_out ;

368 assign pciu_ad_load_out = pcit_sm_ad_load_out ;

369 assign pciu_ad_load_on_transfer_out = pcit_sm_ad_load_on_transfer_out ;

370 assign pciu_pciif_ad_out = pcit_sm_ad_out ;

371 assign pciu_pciif_ad_en_out = pcit_sm_ad_en_out ;

372 assign pciu_pciif_tabort_set_out = pcit_sm_target_abort_set_out ;

373

374 wire pcit_if_addr_claim_out ;

375 wire [31:0] pcit_if_data_out ;

376 wire pcit_if_same_read_out ;

377 wire pcit_if_norm_access_to_config_out ;

378 wire pcit_if_read_completed_out ;

379 wire pcit_if_read_processing_out ;

380 wire pcit_if_target_abort_out ;

381 wire pcit_if_disconect_wo_data_out ;

382 wire pcit_if_disconect_w_data_out ;

383 wire pcit_if_pciw_fifo_full_out ;

384 wire pcit_if_pcir_fifo_data_err_out ;

385 wire pcit_if_wbw_fifo_empty_out ;

386 wire pcit_if_wbu_del_read_comp_pending_out ;

387 wire pcit_if_req_out ;

388 wire pcit_if_done_out ;

389 wire pcit_if_in_progress_out ;

390 wire [31:0] pcit_if_addr_out ;

391 wire [3:0] pcit_if_be_out ;

392 wire pcit_if_we_out ;

393 wire [3:0] pcit_if_bc_out ;

394 wire pcit_if_burst_ok_out ;

395 wire pcit_if_pcir_fifo_renable_out ;

396 wire pcit_if_pcir_fifo_flush_out ;

397 wire pcit_if_pciw_fifo_wenable_out ;

398 wire [31:0] pcit_if_pciw_fifo_addr_data_out ;

399 wire [3:0] pcit_if_pciw_fifo_cbe_out ;

400 wire [3:0] pcit_if_pciw_fifo_control_out ;

401 wire [11:0] pcit_if_conf_addr_out ;

402 wire [31:0] pcit_if_conf_data_out ;

403 wire [3:0] pcit_if_conf_be_out ;

404 wire pcit_if_conf_we_out ;

405 wire pcit_if_conf_re_out ;

406

407 // pci target state machine outputs

408 // pci interface signals

409 assign pciu_conf_offset_out = pcit_if_conf_addr_out ;

410 assign pciu_conf_renable_out = pcit_if_conf_re_out ;

411 assign pciu_conf_wenable_out = pcit_if_conf_we_out ;

412 assign pciu_conf_be_out = pcit_if_conf_be_out ;

413 assign pciu_conf_data_out = pcit_if_conf_data_out ;

414

415 // wishbone master state machine outputs

416 wire wbm_sm_wb_read_done ;

417 wire wbm_sm_write_attempt ;

418 wire wbm_sm_pcir_fifo_wenable_out ;

419 wire [31:0] wbm_sm_pcir_fifo_data_out ;

420 wire [3:0] wbm_sm_pcir_fifo_be_out ;

421 wire [3:0] wbm_sm_pcir_fifo_control_out ;

422 wire wbm_sm_pciw_fifo_renable_out ;

423 wire wbm_sm_pci_error_sig_out ;

424 wire [3:0] wbm_sm_pci_error_bc ;

425 wire wbm_sm_write_rty_cnt_exp_out ;

426 wire wbm_sm_error_source_out ;

427 wire wbm_sm_read_rty_cnt_exp_out ;

428 wire wbm_sm_cyc_out ;

429 wire wbm_sm_stb_out ;

430 wire wbm_sm_we_out ;

431 wire [2:0] wbm_sm_cti_out ;

432 wire [1:0] wbm_sm_bte_out ;

433 wire [3:0] wbm_sm_sel_out ;

434 wire [31:0] wbm_sm_adr_out ;

435 wire [31:0] wbm_sm_mdata_out ;

436

437 assign pciu_err_addr_out = wbm_sm_adr_out ;

438 assign pciu_err_bc_out = wbm_sm_pci_error_bc ;

439 assign pciu_err_data_out = wbm_sm_mdata_out ;

440 assign pciu_err_be_out = ~wbm_sm_sel_out ;

441 assign pciu_err_signal_out = wbm_sm_pci_error_sig_out ;

442 assign pciu_err_source_out = wbm_sm_error_source_out ;

443 assign pciu_err_rty_exp_out = wbm_sm_write_rty_cnt_exp_out ;

444

445 assign pciu_wbm_adr_o = wbm_sm_adr_out ;

446 assign pciu_wbm_dat_o = wbm_sm_mdata_out ;

447 assign pciu_wbm_cyc_o = wbm_sm_cyc_out ;

448 assign pciu_wbm_stb_o = wbm_sm_stb_out ;

449 assign pciu_wbm_we_o = wbm_sm_we_out ;

450 assign pciu_wbm_cti_o = wbm_sm_cti_out ;

451 assign pciu_wbm_bte_o = wbm_sm_bte_out ;

452 assign pciu_wbm_sel_o = wbm_sm_sel_out ;

453

454 // pciw_pcir fifo outputs

455

456 // pciw_fifo_outputs:

457 wire [31:0] fifos_pciw_addr_data_out ;

458 wire [3:0] fifos_pciw_cbe_out ;

459 wire [3:0] fifos_pciw_control_out ;

460 wire fifos_pciw_three_left_out ;

461 wire fifos_pciw_two_left_out ;

462 wire fifos_pciw_almost_full_out ;

463 wire fifos_pciw_full_out ;

464 wire fifos_pciw_almost_empty_out ;

465 wire fifos_pciw_empty_out ;

466 wire fifos_pciw_transaction_ready_out ;

467

468 assign pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt;

469

470 // pcir_fifo_outputs

471 wire [31:0] fifos_pcir_data_out ;

472 wire [3:0] fifos_pcir_be_out ;

473 wire [3:0] fifos_pcir_control_out ;

474 wire fifos_pcir_almost_empty_out ;

475 wire fifos_pcir_empty_out ;

476

477 // delayed transaction logic outputs

478 wire [31:0] del_sync_addr_out ;

479 wire [3:0] del_sync_be_out ;

480 wire del_sync_we_out ;

481 wire del_sync_comp_req_pending_out ;

482 wire del_sync_comp_comp_pending_out ;

483 wire del_sync_req_req_pending_out ;

484 wire del_sync_req_comp_pending_out ;

485 wire [3:0] del_sync_bc_out ;

486 wire del_sync_status_out ;

487 wire del_sync_comp_flush_out ;

488 wire del_sync_burst_out ;

489

490 assign pciu_pci_drcomp_pending_out = del_sync_comp_comp_pending_out ;

491

492 // WISHBONE master interface inputs

493 wire wbm_sm_pci_tar_read_request = del_sync_comp_req_pending_out ;

494 wire [31:0] wbm_sm_pci_tar_address = del_sync_addr_out ;

495 wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ;

496 wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ;

497 wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ;

498 wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ;

499 wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ;

500 wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ;

501 wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ;

502 wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ;

503 wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;

504 wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;

505 wire wbm_sm_pciw_fifo_transaction_ready_in = fifos_pciw_transaction_ready_out ;

506 wire [31:0] wbm_sm_mdata_in = pciu_wbm_dat_i ;

507 wire wbm_sm_ack_in = pciu_wbm_ack_i ;

508 wire wbm_sm_rty_in = pciu_wbm_rty_i ;

509 wire wbm_sm_err_in = pciu_wbm_err_i ;

510

511 // WISHBONE master interface instantiation

512 pci_wb_master wishbone_master

513 (

514 .wb_clock_in (wb_clock_in),

515 .reset_in (reset_in),

516 .pci_tar_read_request (wbm_sm_pci_tar_read_request), //in

517 .pci_tar_address (wbm_sm_pci_tar_address), //in

518 .pci_tar_cmd (wbm_sm_pci_tar_cmd), //in

519 .pci_tar_be (wbm_sm_pci_tar_be), //in

520 .pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in

521 .pci_cache_line_size (wbm_sm_pci_cache_line_size), //in

522 .cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in),

523 .wb_read_done_out (wbm_sm_wb_read_done), //out

524 .w_attempt (wbm_sm_write_attempt), //out

525 .pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out),

526 .pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out),

527 .pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out),

528 .pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out),

529 .pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out),

530 .pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in),

531 .pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in),

532 .pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in),

533 .pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in),

534 .pciw_fifo_empty_in (wbm_sm_pciw_fifo_empty_in),

535 .pciw_fifo_transaction_ready_in (wbm_sm_pciw_fifo_transaction_ready_in),

536 .pci_error_sig_out (wbm_sm_pci_error_sig_out),

537 .pci_error_bc (wbm_sm_pci_error_bc),

538 .write_rty_cnt_exp_out (wbm_sm_write_rty_cnt_exp_out),

539 .error_source_out (wbm_sm_error_source_out),

540 .read_rty_cnt_exp_out (wbm_sm_read_rty_cnt_exp_out),

541 .wb_cyc_o (wbm_sm_cyc_out),

542 .wb_stb_o (wbm_sm_stb_out),

543 .wb_we_o (wbm_sm_we_out),

544 .wb_cti_o (wbm_sm_cti_out),

545 .wb_bte_o (wbm_sm_bte_out),

546 .wb_sel_o (wbm_sm_sel_out),

547 .wb_adr_o (wbm_sm_adr_out),

548 .wb_dat_i (wbm_sm_mdata_in),

549 .wb_dat_o (wbm_sm_mdata_out),

550 .wb_ack_i (wbm_sm_ack_in),

551 .wb_rty_i (wbm_sm_rty_in),

552 .wb_err_i (wbm_sm_err_in)

553 );

554

555 // pciw_pcir_fifos inputs

556 // PCIW_FIFO inputs

557 wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ;

558 wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ;

559 wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ;

560 wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ;

561 wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ;

562 //wire fifos_pciw_flush_in = 1'b0 ; // flush not used for write fifo

563

564 // PCIR_FIFO inputs

565 wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ;

566 wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ;

567 wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ;

568 wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ;

569 wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ;

570 wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ;

571

572 // PCIW_FIFO and PCIR_FIFO instantiation

573 pci_pciw_pcir_fifos fifos

574 (

575 .wb_clock_in (wb_clock_in),

576 .pci_clock_in (pci_clock_in),

577 .reset_in (reset_in),

578 .pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!!

579 .pciw_addr_data_in (fifos_pciw_addr_data_in), //for PCI Target !!!

580 .pciw_cbe_in (fifos_pciw_cbe_in), //for PCI Target !!!

581 .pciw_control_in (fifos_pciw_control_in), //for PCI Target !!!

582 .pciw_renable_in (fifos_pciw_renable_in),

583 .pciw_addr_data_out (fifos_pciw_addr_data_out),

584 .pciw_cbe_out (fifos_pciw_cbe_out),

585 .pciw_control_out (fifos_pciw_control_out),

586 // .pciw_flush_in (fifos_pciw_flush_in), // flush not used for write fifo

587 .pciw_three_left_out (fifos_pciw_three_left_out), //for PCI Target !!!

588 .pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!!

589 .pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!!

590 .pciw_full_out (fifos_pciw_full_out), //for PCI Target !!!

591 .pciw_almost_empty_out (fifos_pciw_almost_empty_out),

592 .pciw_empty_out (fifos_pciw_empty_out),

593 .pciw_transaction_ready_out (fifos_pciw_transaction_ready_out),

594 .pcir_wenable_in (fifos_pcir_wenable_in),

595 .pcir_data_in (fifos_pcir_data_in),

596 .pcir_be_in (fifos_pcir_be_in),

597 .pcir_control_in (fifos_pcir_control_in),

598 .pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!!

599 .pcir_data_out (fifos_pcir_data_out), //for PCI Target !!!

600 .pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!

601 .pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!

602 .pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!

603 .pcir_full_out (),

604 .pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!

605 .pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!

606 .pcir_transaction_ready_out ()

607

608 `ifdef PCI_BIST

609 ,

610 .mbist_si_i (mbist_si_i),

611 .mbist_so_o (mbist_so_o),

612 .mbist_ctrl_i (mbist_ctrl_i)

613 `endif

614 ) ;

615

616 // delayed transaction logic inputs

617 wire del_sync_req_in = pcit_if_req_out ;

618 wire del_sync_comp_in = wbm_sm_wb_read_done ;

619 wire del_sync_done_in = pcit_if_done_out ;

620 wire del_sync_in_progress_in = pcit_if_in_progress_out ;

621 wire [31:0] del_sync_addr_in = pcit_if_addr_out ;

622 wire [3:0] del_sync_be_in = pcit_if_be_out ;

623 wire del_sync_we_in = pcit_if_we_out ;

624 wire [3:0] del_sync_bc_in = pcit_if_bc_out ;

625 wire del_sync_status_in = 1'b0 ;

626 wire del_sync_burst_in = pcit_if_burst_ok_out ;

627 wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ;

628

629 // delayed transaction logic instantiation

630 pci_delayed_sync del_sync

631 (

632 .reset_in (reset_in),

633 .req_clk_in (pci_clock_in),

634 .comp_clk_in (wb_clock_in),

635 .req_in (del_sync_req_in),

636 .comp_in (del_sync_comp_in),

637 .done_in (del_sync_done_in),

638 .in_progress_in (del_sync_in_progress_in),

639 .comp_req_pending_out (del_sync_comp_req_pending_out),

640 .comp_comp_pending_out (del_sync_comp_comp_pending_out),

641 .req_req_pending_out (del_sync_req_req_pending_out),

642 .req_comp_pending_out (del_sync_req_comp_pending_out),

643 .addr_in (del_sync_addr_in),

644 .be_in (del_sync_be_in),

645 .addr_out (del_sync_addr_out),

646 .be_out (del_sync_be_out),

647 .we_in (del_sync_we_in),

648 .we_out (del_sync_we_out),

649 .bc_in (del_sync_bc_in),

650 .bc_out (del_sync_bc_out),

651 .status_in (del_sync_status_in),

652 .status_out (del_sync_status_out),

653 .comp_flush_out (del_sync_comp_flush_out),

654 .burst_in (del_sync_burst_in),

655 .burst_out (del_sync_burst_out),

656 .retry_expired_in (del_sync_retry_expired_in)

657 );

658

659 // pci target interface inputs

660 wire [31:0] pcit_if_address_in = pcit_sm_address_out ;

661 wire [3:0] pcit_if_bc_in = pcit_sm_bc_out ;

662 wire pcit_if_bc0_in = pcit_sm_bc0_out ;

663 wire [31:0] pcit_if_data_in = pcit_sm_data_out ;

664 wire [3:0] pcit_if_be_in = pcit_sm_be_out ;

665 wire [3:0] pcit_if_next_be_in = pcit_sm_next_be_out ;

666 wire pcit_if_req_in = pcit_sm_req_out ;

667 wire pcit_if_rdy_in = pcit_sm_rdy_out ;

668 wire pcit_if_addr_phase_in = pcit_sm_addr_phase_out ;

669 wire pcit_if_bckp_devsel_in = pcit_sm_bckp_devsel_out ;

670 wire pcit_if_bckp_trdy_in = pcit_sm_bckp_trdy_out ;

671 wire pcit_if_bckp_stop_in = pcit_sm_bckp_stop_out ;

672 wire pcit_if_last_reg_in = pcit_sm_last_reg_out ;

673 wire pcit_if_frame_reg_in = pcit_sm_frame_reg_out ;

674 wire pcit_if_fetch_pcir_fifo_in = pcit_sm_fetch_pcir_fifo_out ;

675 wire pcit_if_load_medium_reg_in = pcit_sm_load_medium_reg_out ;

676 wire pcit_if_sel_fifo_mreg_in = pcit_sm_sel_fifo_mreg_out ;

677 wire pcit_if_sel_conf_fifo_in = pcit_sm_sel_conf_fifo_out ;

678 wire pcit_if_load_to_pciw_fifo_in = pcit_sm_load_to_pciw_fifo_out ;

679 wire pcit_if_load_to_conf_in = pcit_sm_load_to_conf_out ;

680 wire pcit_if_req_req_pending_in = del_sync_req_req_pending_out ;

681 wire pcit_if_req_comp_pending_in = del_sync_req_comp_pending_out ;

682 wire pcit_if_status_in = del_sync_status_out ;

683 wire [31:0] pcit_if_strd_addr_in = del_sync_addr_out ;

684 wire [3:0] pcit_if_strd_bc_in = del_sync_bc_out ;

685 wire pcit_if_comp_flush_in = del_sync_comp_flush_out ;

686 wire [31:0] pcit_if_pcir_fifo_data_in = fifos_pcir_data_out ;

687 wire [3:0] pcit_if_pcir_fifo_be_in = fifos_pcir_be_out ;

688 wire [3:0] pcit_if_pcir_fifo_control_in = fifos_pcir_control_out ;

689 wire pcit_if_pcir_fifo_almost_empty_in = fifos_pcir_almost_empty_out ;

690 wire pcit_if_pcir_fifo_empty_in = fifos_pcir_empty_out ;

691 wire pcit_if_pciw_fifo_three_left_in = fifos_pciw_three_left_out ;

692 wire pcit_if_pciw_fifo_two_left_in = fifos_pciw_two_left_out ;

693 wire pcit_if_pciw_fifo_almost_full_in = fifos_pciw_almost_full_out ;

694 wire pcit_if_pciw_fifo_full_in = fifos_pciw_full_out ;

695 wire pcit_if_wbw_fifo_empty_in = pciu_wbw_fifo_empty_in ;

696 wire pcit_if_wbu_del_read_comp_pending_in = pciu_wbu_del_read_comp_pending_in ;

697 wire [31:0] pcit_if_conf_data_in = pciu_conf_data_in ;

698 wire pcit_if_mem_enable_in = pciu_mem_enable_in ;

699 wire pcit_if_io_enable_in = pciu_io_enable_in ;

700 wire pcit_if_mem_io_addr_space0_in = pciu_map_in[0] ;

701 wire pcit_if_mem_io_addr_space1_in = pciu_map_in[1] ;

702 wire pcit_if_mem_io_addr_space2_in = pciu_map_in[2] ;

703 wire pcit_if_mem_io_addr_space3_in = pciu_map_in[3] ;

704 wire pcit_if_mem_io_addr_space4_in = pciu_map_in[4] ;

705 wire pcit_if_mem_io_addr_space5_in = pciu_map_in[5] ;

706 wire pcit_if_pre_fetch_en0_in = pciu_pref_en_in[0] ;

707 wire pcit_if_pre_fetch_en1_in = pciu_pref_en_in[1] ;

708 wire pcit_if_pre_fetch_en2_in = pciu_pref_en_in[2] ;

709 wire pcit_if_pre_fetch_en3_in = pciu_pref_en_in[3] ;

710 wire pcit_if_pre_fetch_en4_in = pciu_pref_en_in[4] ;

711 wire pcit_if_pre_fetch_en5_in = pciu_pref_en_in[5] ;

712 wire [(pci_ba0_width - 1):0] pcit_if_pci_base_addr0_in = pciu_bar0_in ;

713 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr1_in = pciu_bar1_in ;

714 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr2_in = pciu_bar2_in ;

715 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr3_in = pciu_bar3_in ;

716 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr4_in = pciu_bar4_in ;

717 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr5_in = pciu_bar5_in ;

718 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask0_in = pciu_am0_in ;

719 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask1_in = pciu_am1_in ;

720 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask2_in = pciu_am2_in ;

721 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask3_in = pciu_am3_in ;

722 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask4_in = pciu_am4_in ;

723 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask5_in = pciu_am5_in ;

724 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr0_in = pciu_ta0_in ;

725 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr1_in = pciu_ta1_in ;

726 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr2_in = pciu_ta2_in ;

727 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr3_in = pciu_ta3_in ;

728 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr4_in = pciu_ta4_in ;

729 wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr5_in = pciu_ta5_in ;

730 wire pcit_if_addr_tran_en0_in = pciu_at_en_in[0] ;

731 wire pcit_if_addr_tran_en1_in = pciu_at_en_in[1] ;

732 wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ;

733 wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ;

734 wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ;

735 wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ;

736

737 pci_target32_interface pci_target_if

738 (

739 .clk_in (pci_clock_in),

740 .reset_in (reset_in),

741 .address_in (pcit_if_address_in),

742 .addr_claim_out (pcit_if_addr_claim_out),

743 .bc_in (pcit_if_bc_in),

744 .bc0_in (pcit_if_bc0_in),

745 .data_in (pcit_if_data_in),

746 .data_out (pcit_if_data_out),

747 .be_in (pcit_if_be_in),

748 .next_be_in (pcit_if_next_be_in),

749 .req_in (pcit_if_req_in),

750 .rdy_in (pcit_if_rdy_in),

751 .addr_phase_in (pcit_if_addr_phase_in),

752 .bckp_devsel_in (pcit_if_bckp_devsel_in),

753 .bckp_trdy_in (pcit_if_bckp_trdy_in),

754 .bckp_stop_in (pcit_if_bckp_stop_in),

755 .last_reg_in (pcit_if_last_reg_in),

756 .frame_reg_in (pcit_if_frame_reg_in),

757 .fetch_pcir_fifo_in (pcit_if_fetch_pcir_fifo_in),

758 .load_medium_reg_in (pcit_if_load_medium_reg_in),

759 .sel_fifo_mreg_in (pcit_if_sel_fifo_mreg_in),

760 .sel_conf_fifo_in (pcit_if_sel_conf_fifo_in),

761 .load_to_pciw_fifo_in (pcit_if_load_to_pciw_fifo_in),

762 .load_to_conf_in (pcit_if_load_to_conf_in),

763 .same_read_out (pcit_if_same_read_out),

764 .norm_access_to_config_out (pcit_if_norm_access_to_config_out),

765 .read_completed_out (pcit_if_read_completed_out),

766 .read_processing_out (pcit_if_read_processing_out),

767 .target_abort_out (pcit_if_target_abort_out),

768 .disconect_wo_data_out (pcit_if_disconect_wo_data_out),

769 .disconect_w_data_out (pcit_if_disconect_w_data_out),

770 .pciw_fifo_full_out (pcit_if_pciw_fifo_full_out),

771 .pcir_fifo_data_err_out (pcit_if_pcir_fifo_data_err_out),

772 .wbw_fifo_empty_out (pcit_if_wbw_fifo_empty_out),

773 .wbu_del_read_comp_pending_out (pcit_if_wbu_del_read_comp_pending_out),

774 .req_out (pcit_if_req_out),

775 .done_out (pcit_if_done_out),

776 .in_progress_out (pcit_if_in_progress_out),

777 .req_req_pending_in (pcit_if_req_req_pending_in),

778 .req_comp_pending_in (pcit_if_req_comp_pending_in),

779 .addr_out (pcit_if_addr_out),

780 .be_out (pcit_if_be_out),

781 .we_out (pcit_if_we_out),

782 .bc_out (pcit_if_bc_out),

783 .burst_ok_out (pcit_if_burst_ok_out),

784 .strd_addr_in (pcit_if_strd_addr_in),

785 .strd_bc_in (pcit_if_strd_bc_in),

786 .status_in (pcit_if_status_in),

787 .comp_flush_in (pcit_if_comp_flush_in),

788 .pcir_fifo_renable_out (pcit_if_pcir_fifo_renable_out),

789 .pcir_fifo_data_in (pcit_if_pcir_fifo_data_in),

790 .pcir_fifo_be_in (pcit_if_pcir_fifo_be_in),

791 .pcir_fifo_control_in (pcit_if_pcir_fifo_control_in),

792 .pcir_fifo_flush_out (pcit_if_pcir_fifo_flush_out),

793 .pcir_fifo_almost_empty_in (pcit_if_pcir_fifo_almost_empty_in),

794 .pcir_fifo_empty_in (pcit_if_pcir_fifo_empty_in),

795 .pciw_fifo_wenable_out (pcit_if_pciw_fifo_wenable_out),

796 .pciw_fifo_addr_data_out (pcit_if_pciw_fifo_addr_data_out),

797 .pciw_fifo_cbe_out (pcit_if_pciw_fifo_cbe_out),

798 .pciw_fifo_control_out (pcit_if_pciw_fifo_control_out),

799 .pciw_fifo_three_left_in (pcit_if_pciw_fifo_three_left_in),

800 .pciw_fifo_two_left_in (pcit_if_pciw_fifo_two_left_in),

801 .pciw_fifo_almost_full_in (pcit_if_pciw_fifo_almost_full_in),

802 .pciw_fifo_full_in (pcit_if_pciw_fifo_full_in),

803 .wbw_fifo_empty_in (pcit_if_wbw_fifo_empty_in),

804 .wbu_del_read_comp_pending_in (pcit_if_wbu_del_read_comp_pending_in),

805 .conf_addr_out (pcit_if_conf_addr_out),

806 .conf_data_out (pcit_if_conf_data_out),

807 .conf_data_in (pcit_if_conf_data_in),

808 .conf_be_out (pcit_if_conf_be_out),

809 .conf_we_out (pcit_if_conf_we_out),

810 .conf_re_out (pcit_if_conf_re_out),

811 .mem_enable_in (pcit_if_mem_enable_in),

812 .io_enable_in (pcit_if_io_enable_in),

813 .mem_io_addr_space0_in (pcit_if_mem_io_addr_space0_in),

814 .mem_io_addr_space1_in (pcit_if_mem_io_addr_space1_in),

815 .mem_io_addr_space2_in (pcit_if_mem_io_addr_space2_in),

816 .mem_io_addr_space3_in (pcit_if_mem_io_addr_space3_in),

817 .mem_io_addr_space4_in (pcit_if_mem_io_addr_space4_in),

818 .mem_io_addr_space5_in (pcit_if_mem_io_addr_space5_in),

819 .pre_fetch_en0_in (pcit_if_pre_fetch_en0_in),

820 .pre_fetch_en1_in (pcit_if_pre_fetch_en1_in),

821 .pre_fetch_en2_in (pcit_if_pre_fetch_en2_in),

822 .pre_fetch_en3_in (pcit_if_pre_fetch_en3_in),

823 .pre_fetch_en4_in (pcit_if_pre_fetch_en4_in),

824 .pre_fetch_en5_in (pcit_if_pre_fetch_en5_in),

825 .pci_base_addr0_in (pcit_if_pci_base_addr0_in),

826 .pci_base_addr1_in (pcit_if_pci_base_addr1_in),

827 .pci_base_addr2_in (pcit_if_pci_base_addr2_in),

828 .pci_base_addr3_in (pcit_if_pci_base_addr3_in),

829 .pci_base_addr4_in (pcit_if_pci_base_addr4_in),

830 .pci_base_addr5_in (pcit_if_pci_base_addr5_in),

831 .pci_addr_mask0_in (pcit_if_pci_addr_mask0_in),

832 .pci_addr_mask1_in (pcit_if_pci_addr_mask1_in),

833 .pci_addr_mask2_in (pcit_if_pci_addr_mask2_in),

834 .pci_addr_mask3_in (pcit_if_pci_addr_mask3_in),

835 .pci_addr_mask4_in (pcit_if_pci_addr_mask4_in),

836 .pci_addr_mask5_in (pcit_if_pci_addr_mask5_in),

837 .pci_tran_addr0_in (pcit_if_pci_tran_addr0_in),

838 .pci_tran_addr1_in (pcit_if_pci_tran_addr1_in),

839 .pci_tran_addr2_in (pcit_if_pci_tran_addr2_in),

840 .pci_tran_addr3_in (pcit_if_pci_tran_addr3_in),

841 .pci_tran_addr4_in (pcit_if_pci_tran_addr4_in),

842 .pci_tran_addr5_in (pcit_if_pci_tran_addr5_in),

843 .addr_tran_en0_in (pcit_if_addr_tran_en0_in),

844 .addr_tran_en1_in (pcit_if_addr_tran_en1_in),

845 .addr_tran_en2_in (pcit_if_addr_tran_en2_in),

846 .addr_tran_en3_in (pcit_if_addr_tran_en3_in),

847 .addr_tran_en4_in (pcit_if_addr_tran_en4_in),

848 .addr_tran_en5_in (pcit_if_addr_tran_en5_in)

849 ) ;

850

851 // pci target state machine inputs

852 wire pcit_sm_frame_in = pciu_pciif_frame_in ;

853 wire pcit_sm_irdy_in = pciu_pciif_irdy_in ;

854 wire pcit_sm_idsel_in = pciu_pciif_idsel_in ;

855 wire pcit_sm_frame_reg_in = pciu_pciif_frame_reg_in ;

856 wire pcit_sm_irdy_reg_in = pciu_pciif_irdy_reg_in ;

857 wire pcit_sm_idsel_reg_in = pciu_pciif_idsel_reg_in ;

858 wire [31:0] pcit_sm_ad_reg_in = pciu_pciif_ad_reg_in ;

859 wire [3:0] pcit_sm_cbe_reg_in = pciu_pciif_cbe_reg_in ;

860 wire [3:0] pcit_sm_cbe_in = pciu_pciif_cbe_in ;

861 wire pcit_sm_bckp_trdy_en_in = pciu_pciif_bckp_trdy_en_in ;

862 wire pcit_sm_bckp_devsel_in = pciu_pciif_bckp_devsel_in ;

863 wire pcit_sm_bckp_trdy_in = pciu_pciif_bckp_trdy_in ;

864 wire pcit_sm_bckp_stop_in = pciu_pciif_bckp_stop_in ;

865 wire pcit_sm_addr_claim_in = pcit_if_addr_claim_out ;

866 wire [31:0] pcit_sm_data_in = pcit_if_data_out ;

867 wire pcit_sm_same_read_in = pcit_if_same_read_out ;

868 wire pcit_sm_norm_access_to_config_in = pcit_if_norm_access_to_config_out ;

869 wire pcit_sm_read_completed_in = pcit_if_read_completed_out ;

870 wire pcit_sm_read_processing_in = pcit_if_read_processing_out ;

871 wire pcit_sm_target_abort_in = pcit_if_target_abort_out ;

872 wire pcit_sm_disconect_wo_data_in = pcit_if_disconect_wo_data_out ;

873 wire pcit_sm_disconect_w_data_in = pcit_if_disconect_w_data_out ;

874 wire pcit_sm_pciw_fifo_full_in = pcit_if_pciw_fifo_full_out ;

875 wire pcit_sm_pcir_fifo_data_err_in = pcit_if_pcir_fifo_data_err_out ;

876 wire pcit_sm_wbw_fifo_empty_in = pcit_if_wbw_fifo_empty_out ;

877 wire pcit_sm_wbu_del_read_comp_pending_in = pcit_if_wbu_del_read_comp_pending_out ;

878 wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ;

879 wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ;

880 wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ;

881

882

883 pci_target32_sm pci_target_sm

884 (

885 .clk_in (pci_clock_in),

886 .reset_in (reset_in),

887 .pci_frame_in (pcit_sm_frame_in),

888 .pci_irdy_in (pcit_sm_irdy_in),

889 .pci_idsel_in (pcit_sm_idsel_in),

890 .pci_frame_reg_in (pcit_sm_frame_reg_in),

891 .pci_irdy_reg_in (pcit_sm_irdy_reg_in),

892 .pci_idsel_reg_in (pcit_sm_idsel_reg_in),

893 .pci_trdy_out (pcit_sm_trdy_out),

894 .pci_stop_out (pcit_sm_stop_out),

895 .pci_devsel_out (pcit_sm_devsel_out),

896 .pci_trdy_en_out (pcit_sm_trdy_en_out),

897 .pci_stop_en_out (pcit_sm_stop_en_out),

898 .pci_devsel_en_out (pcit_sm_devsel_en_out),

899 .ad_load_out (pcit_sm_ad_load_out),

900 .ad_load_on_transfer_out (pcit_sm_ad_load_on_transfer_out),

901 .pci_ad_reg_in (pcit_sm_ad_reg_in),

902 .pci_ad_out (pcit_sm_ad_out),

903 .pci_ad_en_out (pcit_sm_ad_en_out),

904 .pci_cbe_reg_in (pcit_sm_cbe_reg_in),

905 .pci_cbe_in (pcit_sm_cbe_in),

906 .bckp_trdy_en_in (pcit_sm_bckp_trdy_en_in),

907 .bckp_devsel_in (pcit_sm_bckp_devsel_in),

908 .bckp_trdy_in (pcit_sm_bckp_trdy_in),

909 .bckp_stop_in (pcit_sm_bckp_stop_in),

910 .pci_trdy_reg_in (pcit_sm_trdy_reg_in),

911 .pci_stop_reg_in (pcit_sm_stop_reg_in),

912 .address_out (pcit_sm_address_out),

913 .addr_claim_in (pcit_sm_addr_claim_in),

914 .bc_out (pcit_sm_bc_out),

915 .bc0_out (pcit_sm_bc0_out),

916 .data_out (pcit_sm_data_out),

917 .data_in (pcit_sm_data_in),

918 .be_out (pcit_sm_be_out),

919 .next_be_out (pcit_sm_next_be_out),

920 .req_out (pcit_sm_req_out),

921 .rdy_out (pcit_sm_rdy_out),

922 .addr_phase_out (pcit_sm_addr_phase_out),

923 .bckp_devsel_out (pcit_sm_bckp_devsel_out),

924 .bckp_trdy_out (pcit_sm_bckp_trdy_out),

925 .bckp_stop_out (pcit_sm_bckp_stop_out),

926 .last_reg_out (pcit_sm_last_reg_out),

927 .frame_reg_out (pcit_sm_frame_reg_out),

928 .fetch_pcir_fifo_out (pcit_sm_fetch_pcir_fifo_out),

929 .load_medium_reg_out (pcit_sm_load_medium_reg_out),

930 .sel_fifo_mreg_out (pcit_sm_sel_fifo_mreg_out),

931 .sel_conf_fifo_out (pcit_sm_sel_conf_fifo_out),

932 .load_to_pciw_fifo_out (pcit_sm_load_to_pciw_fifo_out),

933 .load_to_conf_out (pcit_sm_load_to_conf_out),

934 .same_read_in (pcit_sm_same_read_in),

935 .norm_access_to_config_in (pcit_sm_norm_access_to_config_in),

936 .read_completed_in (pcit_sm_read_completed_in),

937 .read_processing_in (pcit_sm_read_processing_in),

938 .target_abort_in (pcit_sm_target_abort_in),

939 .disconect_wo_data_in (pcit_sm_disconect_wo_data_in),

940 .disconect_w_data_in (pcit_sm_disconect_w_data_in),

941 .target_abort_set_out (pcit_sm_target_abort_set_out),

942 .pciw_fifo_full_in (pcit_sm_pciw_fifo_full_in),

943 .pcir_fifo_data_err_in (pcit_sm_pcir_fifo_data_err_in),

944 .wbw_fifo_empty_in (pcit_sm_wbw_fifo_empty_in),

945 .wbu_del_read_comp_pending_in (pcit_sm_wbu_del_read_comp_pending_in),

946 .wbu_frame_en_in (pcit_sm_wbu_frame_en_in)

947 ) ;

948

949 endmodule