-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: CONFIG_3CH.VHD

library IEEE;
use IEEE.std_logic_1164.all;

entity CONFIG_3CH is
        port (
                     PCI_CLOCK :in std_logic;
                     PCI_RSTn :in std_logic;
                     AD_REG :in std_logic_vector (31 downto 0);
                     CBE_REGn :in std_logic_vector ( 3 downto 0);
                     CONF_WR_3CH :in std_logic;
                     CONF_DATA_3CH :out std_logic_vector (31 downto 0)
             );
end entity CONFIG_3CH;

architecture CONFIG_3CH_DESIGN of CONFIG_3CH is

 -- PCI Configuration Space Header Addr : HEX 3C --

        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);

        constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
begin

 --*******************************************************************
 --*********** PCI Configuration Space Header "INTERRUPT" ************
 --*******************************************************************

        CONF_MAX_LAT <= X"00";
        CONF_MIN_GNT <= X"00";
        -- CONF_INT_PIN <= X"00"; -- Interrupt -
        CONF_INT_PIN <= X"01"; -- Interrupt A
        -- CONF_INT_PIN <= X"02"; -- Interrupt B
        -- CONF_INT_PIN <= X"03"; -- Interrupt C
        -- CONF_INT_PIN <= X"04"; -- Interrupt D
        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert

        process (PCI_CLOCK,PCI_RSTn)
        begin
                if PCI_RSTn = '0' then
                        CONF_INT_LINE <= (others => '0');

                elsif (rising_edge(PCI_CLOCK)) then
                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
                        end if;
                end if;
        end process;

        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;

end architecture CONFIG_3CH_DESIGN;